Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 22 replies
  • Subscribers 32 subscribers
  • Views 7656 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TM4C1294NCPDT: Proper ADC signal conditioning with op-amp to minimise sampling errors

Peter John
Expert 1470 points
Part Number: TM4C1294NCPDT

Hi there,

The internal ADC of this TM4C129X MCU is sampling a buffered voltage from a voltage divider (having a thermistor) as follows.

I have found that the 12 bit ADC is in error by  about 2-3% (perhaps  80 counts?).   I cannot tolerate more than 0.2% error or 8 counts of error.    I have shown that simply by probing the ADC input pin with a DMM  set to measure voltage that I get the correct ADC value, otherwise it is off by 2-3%.  I presume the DMM is placing a capacitive load on the pin acting as Cs in the ADC Input Equivalency schematic below.  It is not the 10MOhm input impedance of the DMM as I simulated that by inserting a 10MOhm resistor on the ADC pin to GND and that didn't eliminate the error.

The datasheet indicates that the highest value for the external source resistance to any ADC pin is Rs<=500 Ohms (@1MSPS).  No minimum value for Rs was given so I thought I was a clever designer by putting in a very low source resistance in the form of an op-amp (LTC2054) configured with unity gain (voltage follower) - see circuit diagram above.

I think this input circuit has resulted in errors because the settling time (to 0.01% for 12 bit ADC) of the op-amp is much longer (in the order of many tens of us)  than the ADC sampling time of 250ns (@1MSPS)

I have since read much literature on signal conditioning for SAR ADC inputs [1] and it advises an RC filter after the op-amp for BW limiting and to minimise instability as the sampling capacitor charges up.    I put this RC filter before my op-amp !  OK for BW limiting, but no good on limiting instability as the op-amp charges up the SAR ADC sampling cap.  I haven't yet tried inserting those external R and C components after the op-emp yet, and there are penalties if I do from a design change perspective. 

Is there another way for me to solve this problem in firmware rather than in H/W by extending the sampling time of the ADC to be say 100us instead of 250ns ?? I couldn't see an option to do that in the datasheet, only something about adjusting the sample and hold window time "The ADC module provides the capability of programming the sample and hold window of each step in a sequence through the ADC Sample Sequence n Sample and Hold Time (ADCSSTSHn) register." (p.1058)

Here is the ADC input circuit from the datasheet.  My Rs (output resistance of the op-amp) is very low (probably a few ohms), and my Cs is probably only a few pF from parasitic track capacitance.

[1]  Optimise your SAR ADC Design by Bonnie Baker at TI,    Input Drive Circuitry for SAR ADCs,  An Overview of Designing Analog Interface With TMS320F28xx/28xxx DSCs

  • 0
    Expert 1470 points

    I discovered the following function.  ADCClockConfigSet .  Will that have the effect of lengthening the ADC Sample Time from 250ns to say 100us for me to solve my problem ? Or does it just decimate the samples at 1 MSPS and provide every n'th sample to the firmware (in which case that is no good for me)

  • 0
    Guru 117855 points

    In our use of the ADC - across many ARM MCU vendors - we've found that most always - employing a small value, ceramic (bypass) cap (0.01µF) placed as close to the MCU pin(s) as possible - avoids the issue you note.   We note too - that most always - such mixed signal ADC implementations reveal jitter across their 3-4 least significant bits.     (8-16 "suspect counts")

    I believe that - as you fear - all other "attempts" will incur trade-offs...some "worse" than the issue you report.      (it may be possible to "tack" that cap from the op-amp's output to gnd - as "nasty" as that appears - I believe it proves your "best" bet...)

    You may (also) consider the, "speed of response" of your thermistor - and its (potentially) critical placement - so that the thermistor best captures that "point/area" being thermally monitored...     (small mass devices usually provide the fastest response)

  • 0 in reply to cb1_mobile
    Expert 1470 points

    Thanks cb1_mobile.

    While I knew I could work-around this problem by putting an RC after the op-amp, I have only just tried that out after following the calculations for the optimal values of Rs and Cs using the above papers linked to at [1].   In short it worked :)   When I looked at the LTC2054 op-amp datasheet, and estimated its output resistance from the slope of I vs V in figure 20545 G05, I estimated it to be 140 Ohms.  MUCH larger than I expected.  Anyway, that works in my favour as I can use its output resistance to form Rs.  I then calculated Cs to be 0.2nF=200pF.  so I stuck a 220pF cap from the U21 op-amp's output to GND and voila, my error was now <0.2% !

    Cs acts as a charge reservoir for the ADC's SAH cap Csh to get most (~95%) of its charge from .  While about 5% of the charge comes from the op-amp's output in my design which is an acceptable trade-off according to the design notes at [1]..  Cs must be at least 20x Cadc=20x10pF=200pF.

    So that solution didn't come as a huge surprise for me as I predicted that in my first post.  What I am really hoping to do however is to solve this problem in firmware by increasing the acquisition/sampling time of the ADC by 200 times from 250ns to say 50us. Note to others, this sampling time is not the sampling period (which in my case is only a few hundred Hz), but the time the ADC's SAH switch is closed and Csh is charging for.  So...

    Can I programmatically increase the SAR ADC's sampling time from 250ns to 50us ??

    If not then the only way to solve this problem is by tacking on 220pF 0805 caps manually to my op-amp outputs (I have 4 in total), or changing the PCB layout to add them onto the board (risky).

    @cb1_mobile, the thermistors are relatively large (2mm across) so their thermal time constants are in the order of seconds.

  • 0 in reply to Peter John
    Guru 92251 points

    Peter John said:
    What I am really hoping to do however is to solve this problem in firmware by increasing the acquisition/sampling time of the ADC by 200 times from 250ns to say 50us.

    The ADC Sample Sequence n Sample and Hold Time (ADCSSTSHn) register allows control over the ADC Sample and Hold Width. The allowed values are 4, 8, 16, 32, 64, 128, 256. If the ADCSSTSHn was changed from the default Nsh value of 4 to the max Nsh value of 256 the sample and hold time would increase from 250ns to 16us (with a 16 MHz ADC clock).

    The ADC Clock Configuration (ADCCC) register may also be changed to select a different ADC clock that the default 16 MHz from the PIOSC. If the ADC Clock Configuration (ADCCC) register was changed to select the ADC clock as the PLL VCO Clock (480 MHz) / 64 (maximum divisor) then the ADC clock would be slowed to 7.5 MHz. An ADC clock of 7.5 MHz with the maximum Nsh of 256 would result in an ADC sample and hold time of 31 us. That might be sufficient to solve the problem in firmware.

  • 0 in reply to Chester Gillon
    Expert 1470 points
    Thanks Chester ! As I received your post I was actually in the process of trying that out. I'm glad you mentioned the default setting was 4 as I assumed it was 1 but when I look at the value of the constant defined for 4 in adc.h it makes sense that 4 is the default.

    #define ADC_CTL_SHOLD_4 0x00000000 // Sample and hold 4 ADC clocks

    I'll report back once I have an answer.
  • 0 in reply to Chester Gillon
    Expert 1470 points

    I can tentatively say this might have solved the problem.  I'm surprised that the opamp has settled down to 0.01% of its final value (stopped ringing) within 16us.  I thought it might have been longer than that.

    Here is the code I used for my 4 channels to increase the sample and hold time from 250ns to 16us (factor of 256/4=64).  I'll report back if further testing shows I need the H/W fix instead of this firmware fix.

    ADCSequenceStepConfigure(ADC0_BASE, 2, 0, ADC_CTL_CH0 | ADC_CTL_SHOLD_256);
ADCSequenceStepConfigure(ADC0_BASE, 2, 1, ADC_CTL_CH1 | ADC_CTL_SHOLD_256);
ADCSequenceStepConfigure(ADC0_BASE, 2, 2, ADC_CTL_CH2 | ADC_CTL_SHOLD_256);
ADCSequenceStepConfigure(ADC0_BASE, 2, 3, ADC_CTL_CH3 | ADC_CTL_SHOLD_256 | ADC_CTL_IE | ADC_CTL_END);


  • 0 in reply to Chester Gillon
    Guru 117855 points

    Chester Gillon said:
    If the ADC Clock Configuration (ADCCC) register was changed to select the ADC clock as the PLL VCO Clock (480 MHz) / 64 (maximum divisor) then the ADC clock would be slowed to 7.5 MHz.

    Neither firm nor I are "fans" of "4C129" (far too slow & insufficient support for modern displays) yet - the ADC module for the "4C123 (and earlier devices)" has (long) had the requirement for a 16MHz ADC clock.    At minimum - you should reveal the specs (far back w/in the MCU Manual) - to learn if 7.5MHz meets compliance...

    In addition - it would be wise to check the "persistence" of this "fix" over multiple boards - not just one - to establish greater confidence...

    The minimal ADC error you report proves "curious" - such mixed signal devices are noted for, "Less than that level of performance."     As accuracy & precision appear your goal - your management of VDDA and its Gnd demand great consideration as well.      You may wish to perform 8 (or beyond) ADC operations quickly (back to back) - I'd be most surprised if the 3-4 lsb jitter is not present...

  • 0
    Guru 27665 points

    Late to the party but a few points are in order I think

    Peter John said:
    I have found that the 12 bit ADC is in error by  about 2-3% (perhaps  80 counts?).   I cannot tolerate more than 0.2% error or 8 counts of error. 

    That's a not a straightforward requirement, especially for temperature. You've already thrown away half of that in your noted source reference before considering self heating or other error sources at the measurement. That means your A/D reference, conditioning circuitry and A/D itself can only contribute another 0.1%. However your sense resistor already introduces 0.1% error and you have no indication here what your thermistor error is.

    Also, you should read the error specs on the A/D. Look for total unadjusted error and Signal to Noise ratio and read the footnotes.

    And finally your reference makes a difference. I suspect you are using the power supply since you haven't noted using an explicit reference so that's likely somewhere between 0.5% and 5% although it could be as high as 10%.  Even in the unlikely event that you have a 0.1% power supply you still have 0.3% error before considering the A/D and thermistor contributions.

    As cb1 noted and you've discovered you do need a capacitor on the A/D input because of the high speed of the sampling circuit (See #bookshelf for some references). However you do need the RC to cut down your incoming frequencies to below your Nyquist limit as well. You haven't mentioned your sampling frequency so it's hard to judge what the time constant should be. Note you need this even if your source is bandwidth limited. Your op-amp circuit can do your Nyquist filtering but an RC is still recommend, both for stability and to knock back any noise introduced after the op-amp. For the latter case the requirements are usually not as stringent as for the Nyquist filter.

    Peter John said:
    OK for BW limiting, but no good on limiting instability as the op-amp charges up the SAR ADC sampling cap.

     

    Not if you have a resistor in series.

    Robert

    Final note: There are few systems that benefit from temperature accuracy of better than 1C, many can deal with considerably less accuracy. Some, like home heating, don't need better than 1C accuracy but do benefit from better than 1C repeatability.

  • 0 in reply to cb1_mobile
    Guru 27665 points

    cb1_mobile said:
    Chester Gillon
    If the ADC Clock Configuration (ADCCC) register was changed to select the ADC clock as the PLL VCO Clock (480 MHz) / 64 (maximum divisor) then the ADC clock would be slowed to 7.5 MHz.

    Neither firm nor I are "fans" of "4C129" (far too slow & insufficient support for modern displays) yet - the ADC module for the "4C123 (and earlier devices)" has (long) had the requirement for a 16MHz ADC clock.    At minimum - you should reveal the specs (far back w/in the MCU Manual) - to learn if 7.5MHz meets compliance...

    In addition - it would be wise to check the "persistence" of this "fix" over multiple boards - not just one - to establish greater confidence...

    The minimal ADC error you report proves "curious" - such mixed signal devices are noted for, "Less than that level of performance."     As accuracy & precision appear your goal - your management of VDDA and its Gnd demand great consideration as well.      You may wish to perform 8 (or beyond) ADC operations quickly (back to back) - I'd be most surprised if the 3-4 lsb jitter is not present...

    This is in need of a like.

    Robert

  • 0 in reply to Robert Adsett
    Guru 117855 points

    Thank you - thank you very much.

    Such "affirmation" from the master is gratifying - yet unfortunately (those w/"closed/uninspired" mind) have BANNED "LIKE" from this playing field.   (forcing much "extra time/effort" upon those who generously contribute, "blood, sweat, tears" here) - which overwhelm the "care & understanding" of those "ivy towered" (for now) in forum control...)

    Most all MCU programs here aim for (some) element of Control - and a prime demand of Control - is accurate & responsive feedback!     Pity that the forum "crüe" have chosen to disregard such truth...

  • 0 in reply to Robert Adsett
    Expert 1470 points

    Robert Adsett said:

    That's a not a straightforward requirement, especially for temperature. You've already thrown away half of that in your noted source reference before considering self heating or other error sources at the measurement. That means your A/D reference, conditioning circuitry and A/D itself can only contribute another 0.1%. However your sense resistor already introduces 0.1% error and you have no indication here what your thermistor error is.

    Thanks Robert.  I can make things a bit clearer to explain that 0.2%.which I was attributing to the total ADC error of 4LSBs = 4/4096=0.1% + poor signal conditioning error=0.1%

    My total error budget will be 

    (Thermistor resistance error ) + (Thermistor beta error) + (sense resistor error) + (thermistor Vref error) +  (op-amp offset error) + (ADC total error) + (ADC external Vref error) + ( poor signal conditioning )

    = 1% + 0.5% +  0.1% + 0.1% + 3uV (negligible) + (4LSB=0.1%) + 0.1% + 0.1%

    Assuming the errors are uncorrelated I will RSS them together for a total error value of 1.14%.  You linearly added the errors which is unnecessarily harsh (unless you can tell me which errors are correlated).

    Regarding your comments on nyquist filtering, that is taken care of by R90 and C127 in the original schematic I posted. Sampling rate will be 1kHz maximum in case we opt to put some very small and hence fast thermistors in the circuit (I already have some from Amphenol (B07 series) with time constants in the order of 50ms).

    At my work we routinely need temperature accuracies of +/-1.0degC, and sometimes 0.2degC for which we use a Fluke handheld 1524 unit.

  • 0 in reply to cb1_mobile
    Expert 1470 points

    cb1_mobile said:
    You may wish to perform 8 (or beyond) ADC operations quickly (back to back) - I'd be most surprised if the 3-4 lsb jitter is not present...

    I do LPF the results to increase resolution after initially sampling at 1kHz.  I have also tested this firmware solution on 3 units with OK results at one input voltage level.  More testing at multiple voltage levels will happen this week.

    the underlying 3-4LSB error is present, sorry if I suggested otherwise.

  • 0 in reply to Peter John
    Guru 117855 points

    Peter John said:
    I can make things a bit clearer to explain that 0.2%.which I was attributing to the total ADC error of 4LSBs = 4/4096=0.1%

    You did not mean (that!)      Four lsb - as you know - translates to 16 "counts" out of 4096.

    Note too that your "migration" to the less massive thermistor - while faster responding - incurs the penalty of (potentially) increased, "self-heating."

  • 0 in reply to cb1_mobile
    Expert 1470 points

    cb1_mobile said:
    the total ADC error of 4LSBs = 4/4096=0.1%
    You did not mean (that!)      Four lsb - as you know - translates to 16 "counts" out of 4096.

    oops !   that was an embarrassing mistake.  So I am only seeing 4 COUNTS of jitter on the raw ADC value when using a fixed known resistor with no extension leads that would normally run to a thermistor.

    I realise it will be worse than that with leads picking up noise and at other voltages, perhaps as you say up to 3-4LSB.  For me now I only see 2LSBs of jitter (0.1% error), but I need to budget for 16/4096=0.4% error..  Thanks for pointing out the error in my error budget !

    cb1_mobile said:
    Note too that your "migration" to the less massive thermistor - while faster responding - incurs the penalty of (potentially) increased, "self-heating."

    Yes, thank you for that reminder.

  • 0 in reply to Peter John
    Guru 27665 points

    Using a reference does make it a lot easier.

    Peter John said:
    Assuming the errors are uncorrelated I will RSS them together for a total error value of 1.14%.  You linearly added the errors which is unnecessarily harsh (unless you can tell me which errors are correlated).

    This only works for large numbers. Otherwise worst case analysis is correct. Assuming you are not willing to test over operating conditions and filter out non-performing product accordingly.

    The parts you get are not randomly distributed. Unless you have very large numbers you will get subsets of specific batches. These will tend to group around a particular error. Each subset will group differently. You can, in fact, get parts at different ends of the tolerance range for different parts and for the same part you would expect the errors to be correlated. Your calculation is correct for a calculation of some sort of expectation value for the error but not for the worst case, which is what you need to consider.

    Calibration really helps here, since it can knock out the initial offset and gain errors but it will not account for drift in those values. I've been caught by that before when I assumed that a particular part (like other similar parts) had most of its error coming from static sources and it turned out to come from drift.

    Peter John said:
    explain that 0.2%.which I was attributing to the total ADC error of 4LSBs = 4/4096=0.1%

    Did you notice the footnote on that? That places a minimum sampling requirement in order to reach that specification.

    Not really an error source directly but the SNR is likely important as well. and that gives worst case ENOB result of a little over 9.5 bits.

    Peter John said:
    At my work we routinely need temperature accuracies of +/-1.0degC, and sometimes 0.2degC for which we use a Fluke handheld 1524 unit.

    Nice meter. Not cheap.

    Robert

  • 0 in reply to Peter John
    Guru 117855 points

    Still unresolved - "ADC clocked @ 7.5MHz!"     (so advised by "another" - when - in the long past and continuing - ADC clock was spec'ed @ 16MHz!)      I don't know nor use your MCU - rear of that MCU manual (ADC spec section) should properly reveal...

  • 0 in reply to cb1_mobile
    Guru 27665 points

    cb1_mobile said:
    Peter John
    I can make things a bit clearer to explain that 0.2%.which I was attributing to the total ADC error of 4LSBs = 4/4096=0.1%
    You did not mean (that!)      Four lsb - as you know - translates to 16 "counts" out of 4096.

    Actually it is specced in the data sheet as LSB. However one of the error specs is +/-30LSB so it seems likely they actually mean counts.

    Perhaps someone from TI could clarify that they mean counts rather than bits?

    Robert

  • 0 in reply to Robert Adsett
    Guru 117855 points

    Do note that the quote I placed in highlight focused upon "4lsb = 4/4096" - which it does not.    Writer's meaning - as we all know - was 4lsb = "16 counts."
    As to "±30 lsb" - such would seem "questionable" for a (lowly) 12bit device!

    As you surmise - "counts" was (surely) intended (in both cases)...

  • 0 in reply to cb1_mobile
    Guru 92251 points

    cb1_mobile said:
    Neither firm nor I are "fans" of "4C129" (far too slow & insufficient support for modern displays) yet - the ADC module for the "4C123 (and earlier devices)" has (long) had the requirement for a 16MHz ADC clock.    At minimum - you should reveal the specs (far back w/in the MCU Manual) - to learn if 7.5MHz meets compliance...

    Looking at the TM4C1294NCPDT datasheet dated June 18, 2014 shows

    a) ADC Electrical Characteristics listed for a ADC conversion clock frequency of 16MHz or 32MHz.

    b) The maximum ADC conversion clock frequency is 32MHz.

    However, I can't find any mention if the ADC is specified to operate with a conversion clock frequency of other than 16MHz or 32MHz.

  • 0 in reply to Chester Gillon
    Guru 117855 points

    As stated - historically (and w/each/every MCU firm/I have used here - that's > 8) - the suggestion of other than 16MHZ ADC clock - proves WRONG!
    7.5MHz - as suggested - is simply incorrect...   (severe violation of MCU spec!)    

    You may wish to mark that 7.5MHz suggestion as mistaken - so that (others) do not follow such "false path."

  • 0 in reply to Chester Gillon
    Guru 27665 points

    Chester Gillon said:
    However, I can't find any mention if the ADC is specified to operate with a conversion clock frequency of other than 16MHz or 32MHz.

    That is probably a hint.

    IIRC the '123 data sheet mentions that the A/D must be run at 16MHz and the '129 appears to just add a separate 32MHz mode. So that combined with the fact you have no operating specs for frequencies other than 16 or 32MHz strongly suggest to me you should use one of those two barring information to the contrary.

    Robert

  • 0 in reply to Robert Adsett
    Guru 117855 points

    Or - perhaps worse still - may work w/"some lots" - for "some time" - yet not w/"different and/or newer lots" and/or "operating conditions" - over a broader (longer) time spectrum.

    Compliance with device specs - no matter the "Appeals of violation" - is ALWAYS recommended.     Legally - such actions expose the violator - to full and sole penalty - breaking the (usual) "umbrella protection" - acquired thru, "Full vendor-spec compliance..."