• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 2980 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Watchdog cpu reset

dha1
Prodigy 20 points


For my tiva-c microcontroller I have the watchdog timeout configured to 1 sec. After disable of the watchdog trigger function it takes 2 seconds until a cpu reset occurs. What is the correct configuration to get a cpu reset after 1 second?

The watchdog timer can be configured to generate an interrupt to the processor after its first timeout, and to generate a reset signal after its second timeout. Is there a way to get a cpu reset signal after the first timeout?

  • 0
    TI__Guru*** 135355 points
    Hello dha1,

    What TM4C MCU are you using specifically? We have two device families, TM4C123x and TM4C129x, I need to know which you are using to help.

    Also when you say 'after disable', can you clarify how you are disabling and then re-enabling the watchdog?
  • 0 in reply to Ralph Jacobi
    Prodigy 20 points

    Hello Jacobi,

    I'm using the TM4C123x family. With disable I mean stop triggering or stop to reset the watchdog timeout.

  • 0 in reply to dha1
    TI__Guru*** 135355 points

    Hello dha1,

    Okay understood, I wanted to confirm that you are restarting the watchdog fully, because what you are seeing (as you likely noticed) only would occur at the very start of the watchdog.

    The behavior you are seeing is exactly how the watchdog is intended to work based on device specification. I will copy the description of the watchdog timer and then explain further:

    The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
The watchdog interrupt can be programmed to be a non-maskable interrupt (NMI) using the INTTYPE
bit in the WDTCTL register. After the first time-out event, the 32-bit counter is re-loaded with the
value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down
from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock
(WDTLOCK) register is written, which prevents the timer configuration from being inadvertently
altered by software.

If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled by setting the RESEN bit in the WDTCTL register, the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value

    As described, the watchdog generates an interrupt the first time the timer counts down. At this point, the ISR can do one of two things.

    1) Feed the watchdog to keep it happy, and it will run in the background until it is ready to be fed again at the end of the next count down

    2) Ignore the watchdog by not clearing the interrupt, and then when the timer counts down again a second time, it will check if RESEN has been set, and if so, then it will reset the CPU.

    In other words, by design, you need two cycles through the timer to be able to reset the CPU via the Watchdog timeout feature once you start it.

    Once it is running, then it is easier to handle as you just need to not clear the next interrupt you get, but even in this case there are situations where you may need close to 2 seconds to get it process if you decided you wanted to reset immediately after just having cleared the timer.