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DRV8426E: CPL waveform

Yuta Nishie
Genius 4945 points
Part Number: DRV8426E

Hi,

Is my interpretation of the VCPL transition shown in the red frame correct?

Also, please tell me the reason why the voltage becomes constant around 5V in (1) and (4).

(1) High side FET is ON. The source of the High side FET is clamped to the bias voltage of 5V.

(2) High side FET ON. There is a constant current circuit in the VM of the drain of the high side FET, and the voltage is gradually rising.

(3) High side, Low side FET OFF = dead time. Discharge from a 0.022uF capacitor.

(4) Low side FET On. It is clamped to the bias voltage of 5V.

(5) Low side FET On. Discharge from a 0.022uF capacitor. The current decreases as the voltage increases. Therefore, the voltage drop also decreases, and the slope is gentler than (3).

Best Regards,

Nishie

  • 0
    TI__Guru 56650 points

    Nishie,

    When the high side FET is on, VM is shorted to CPL. CPH/CPL capacitor charges the VCP capacitor.

    When the low side FET is on, CPL is shorted to ground. VM source charges the CPH/CPL capacitor.

    When the low side FET and high side FET are both off, CPL is floating. No charge on both capacitors.

    Regards,

    Wang Li

  • 0 in reply to Wang5577
    Genius 4945 points

    Hi Wang Li,

    Thank you for your reply.

    I understood the operating principle of the charge pump.

    I have an additional question.

    Which voltage is 5V in (1)?

    Is the voltage of (2) gradually increasing due to the constant current circuit?

    Best Regards,

    Nishie

  • +1 in reply to Yuta Nishie
    TI__Guru 56650 points

    Nishie,

    The internal DVDD is regulated at 5V. From the test waveform, both high side and low side FETs should be off in region 1. The high side FET's gate voltage should be same as the FET's source (CPL pin) voltage.

    in (2), CPH/CPL capacitor charges the VCP capacitor. According to the waveform, I agree the voltage of (2) gradually increasing is due to the charge current control.

    Regards,

    Wang Li

  • 0 in reply to Wang5577
    Genius 4945 points

    Hi Wang Li,

    Thank you for your reply.

    In the waveforms of (3) and (4), are the High-side FET and Low-side FET in the Off state?

    Best Regards,

    Nishie

  • +1 in reply to Yuta Nishie
    TI__Guru 56650 points

    Nishie,

    In (3) and (4) period, the High-side FET and Low-side FET are both in the Off state first. And then, the low side FET starts turn-on. The low side FET's slow turn-on can also reduce the inrush current to charge CPH/CPL capacitor.

    Best Regards,

    Wang