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DRV8301: About DRV8301 overcurrent protection threshold setting

Annie Liu
Genius 10295 points
Part Number: DRV8301
Other Parts Discussed in Thread: DRV8323R

Hi Team,

Customers want to know how to consider setting the VDS overcurrent protection threshold when using DRV8301? 

Is this protection more sensitive? If it is set to the lowest gear, is it easy to trigger the 8301 overcurrent protection?

Thanks,

Annie

  • 0
    TI__Intellectual 1350 points

    Hi Annie,

    When setting the VDS overcurrent protection threshold, it is important to consider that there can be up to a 20% tolerance across channels for the VDS trip point. Some of the factors that can affect the accuracy of the VDS monitoring are things such as temperature increase (Which increases RDSon resistance), noise in VDS traces, coupling, and drain and source trace parasitic inductance. It is important to note that this scheme is designed as a fail-safe, not as a precise current regulator.

    When considering which VDS threshold to use, it is important to consider the RDSon of the FET’s one would like to use. The overcurrent threshold is calculated with Ohm’s law: VDS Overcurrent Trip current = VDS/RDSon. The VDS threshold voltage can be configured over SPI through bits 6-10 in the OC_ADJ_SET register. The customer may want to take the available VDS voltage settings into consideration when selecting a FET to ensure that the RDSon resistance will allow for the desired overcurrent protection.   

    With regards to the customer’s question about the lowest VDS threshold of 0.06V: This threshold would likely be more sensitive to the factors mentioned earlier (temperature change, noise, coupling etc.) due to the low amount of voltage required to trigger it. For example: a 0.06V threshold would have a much smaller margin for noise than a 2.4V threshold.

    The DRV8301 does not have a dedicated VDRAIN pin like newer devices (see the DRV8323R). This means the high-side MOSFET drain voltage is sensed at PVDD. If the PVDD pin is far away from the MOSFET drains or there is some impedance in the path, the VDS monitor may be falsely triggered by voltage spikes.

    Best,

    Johnny Vallespir