DRV8305-Q1: Questions

Aaron-san

Thank you for your continued support.

Please let me know if you have any update for this.

Regards,

Kura

Hi Kura-san,

Still looking through your questions, please let me give a reply by the end of the week. 

Thanks,
Aaron

Hi Kura-san,

Queston 1: Yes it is okay to input pulse of Hi = 2ms, Lo = 2ms on EN_GATE.

Question 2: tBLANK should start at A when the inputs toggle, I need to confirm with design on this. 

Thanks,
Aaron

Aaron-san

Thank you for your support.

We got additional questions from customer.

Please check following questions.

Question 3: About Fault deglitch time
The deglitch time for Vreg low voltage is listed in the datasheet, but the deglitch time for other Fault type errors is not.
Please tell us the deglitch time of each of the following Fault type errors including Max and Min.
It does not have to be a guaranteed value, but a measured value, a design value, or a theoretical value may be used.
・ PVDD Under voltage 2
・ Charge Pump Undervoltage2
・ LS Gate Supply Undervoltage
・ Charge Pump Overvoltage
・ Charge Pump Overvoltage ABS
・ AVDD Under voltage
・ Overtemperature Shutdown
・ LS Overcurrent (SNS_OCP)
・ Gate Drive Fault (GDF)

Question 4: What are the recommended ranges for P VDD and Fault type errors?
Does a Fault type error occur if PVDD is in the recommended range of 4.4-45V?

Question 5: Regulator PSRR
Please tell me about PSRR of A VDD, VCPH, VCP_LSD.
We would appreciate it if you could give me the frequency characteristics.

Question 6: About internal clock failure
They speculate that this IC has an internal clock and is used for the charge pump operating clock and dead time timer.
If something goes wrong with this internal clock and the frequency becomes faster or slower, what will the IC do?
Will this IC turn off the external FET and keep it in that state?
If this IC keeps the external FET off, will it be notified to the MCU by nFAULT etc.?

About Question2:

If you have any update about question2,please let us know it. (I think you  need to confirm with design on this. )

Regards,

Kura

Hi Kura-san,

I confrimed about question 2 earlier today with design that tBLANK is enforced when inputs toggle, i.e. region A from the previous excel sheet. Going over your questions today. 

Thanks,
Aaron

Hi Kura-san,

Allow me to answer some of the newer questions:

Q3: I need to look up the deglitch times in our internal database, which each fault should have their own deglitch time for min and max value. I will provide this tomorrow. 

Q4: PVDD undervoltage faults occur when PVDD < PVDD_UVLO1 and PVDD_UVLO2. If < PVDD_UVLO2, gate drive outputs are pulled low and gate drive supplies are disabled, but internal logic is enabled. When <PVDD_UVLO1, internal logic is disabled and fault type errors will be invalid due to the logic core being disabled. 

Q5: For any DC supply circuits such as voltage rails, you can calculate variation from the datasheet specifications. Since these are DC supplies and should not have any AC components to the signals, calculating PSRR for these frequency characteristics doesn't really make sense. According to the block diagram of the device, all of these regulators come from PVDD supply, so please check the PSRR of the supply for the PVDD pin. If it is a well regulated supply, there should not be any discernable PSRR from the device. Adding output capacitances for each supply/regulator will help improve DC performance and removing AC components from the signals. 

Q6: The DRV8305-Q1 is not a safety device, which means we do not do any internal clock monitoring or actions when there is an IC clock failure. Many things can go wrong if the clock frequency increases. If it is too high, digital core may not function correctly. If it is too low, the charge pump may not function correctly. There is no intentional turnoff of FETs or the charge pump if this failure occurs. The DRV3245-Q1 is a safety device designed from the DRV8305-Q1, so it has many similar specifications, protections, and timings as we've discussed on this thread before and includes clock monitoring. 

Thanks,
Aaron