• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 30 subscribers
  • Views 384 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8425: nFAULT on Power up

Yuta Nishie
Genius 4955 points
Part Number: DRV8425
Other Parts Discussed in Thread: DRV8886, , DRV8825

Hi,

I found the following article.

https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/979170/boostxl-drv8305evm-drv8305-nfault-on-startup

Does all TI motor drivers get nFAULT asserted by UVLO or CPUV at power up?

For example, do DRV8425 and DRV8886 assert nFAULT?

Best Regards,

Nishie

  • +1
    TI__Guru 56650 points

    Nishie-san,

    Some drivers don't have the charge pump like DRV8825 and DRV8886.

    Yes. DRV8425 and DRV8886 assert nFAULT by UVLO or CPUV. CPUV timing could be different than the power up timing. CPUV could follow the sleep pin timing.

    Regards,

    Wang Li

  • 0 in reply to Wang5577
    Genius 4955 points

    Hi Wang Li-san,

    Thank you for your reply.

    Could you give me the timing chart of VCP and nFAULT when the power is turned on, and the timing chart of CPUV and Sleep pin voltage and nFAULT?

    Does "CPUV timing could be different than the power up timing." mean that the CPUV timing is later than the power up timing because the charge pump voltage rises after the power supply voltage is turned on?

    Also, does "CPUV could follow the sleep pin timing." mean that using High / Low of sleep pin can prevent asserting nFAULT by CPUV?

    Best Regards,

    Nishie

  • +1 in reply to Yuta Nishie
    TI__Guru 56650 points

    Nishie-san,

    After the power supply voltage is turned on and nSLEEP is high, CPUV logic can be active. So, the timing is related to nSLEEP pin timing and UVLO timing. 

    The timing chart of VCP and nFAULT: After twake and ton expired, nFAULT is immediately pulled to low when VCP is lower than CPUV threshold. 

    Yes. the CPUV timing is later than the power up timing because the charge pump voltage rises after the power supply voltage is turned on and nSLEEP is high.

    In sleep mode (nSLEEP in low), all the internal MOSFETs are disabled and the charge pump is disabled. The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device enters sleep mode. The device is brought out of sleep automatically if the nSLEEP pin is brought high. The tWAKE time must elapse before the device is ready for inputs.

    I didn't think we can use High / Low of sleep pin can prevent asserting nFAULT by CPUV because nSLEEP low will put the device in sleep mode. 

    Why do you want to block nFault in CPUV condition?

    Regards,

    Wang Li

  • 0 in reply to Wang5577
    Genius 4955 points

    Hi, Wang Li-san,

    I'm sorry I missed your reply.

    Our customer was concerned about nFAULT when the power was turned on, but the problem was solved.

    Thank you for your support.

    Best Regards,

    Nishie