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DRV8353R: The FAULT pin generates a negative pulse (spike) when the DRV8353 is enabled

Cherry Zhou
Mastermind 22235 points
Part Number: DRV8353R
Other Parts Discussed in Thread: DRV8301, DRV8353

As shown in the following figure, VCC _VM is DC24V, NFAULT pull-up resistor 2.2 k.

When EN pin is enabled (pulled high), the NFAULT pin generates a negative pulse. And then the MCU interrupt was caused, internal data was read through SPI, and there was no specific fault bit, as shown in Figure 2 for the test graph. 

The customer would like to know what is the possible reason for that.

Thanks!

Best Regards,

Cherry Zhou

  • 0
    TI__Mastermind 21805 points

    Hello Cherry,

    When the DRV8353R is powered on or when ENABLE is pulled high, the device clears UVLO. This causes the nFAULT pin to pull low and then high again as the part powers on.

    nFAULT going high indicates that the DRV82353R has successfully powered ON and is ready for communication.

    Thanks,

    Matt

  • 0 in reply to Matt Hein
    TI__Mastermind 22235 points

    Hi Matt,

    Thanks for your reply!

    And the customer finds the other product is enabled without pulses. Four small spikes occur at 80 ms after enable, at a time interval of 80 ms, and this pulse does not trigger an MCU interrupt, as the figure below. May I know what is the possible reason for that?

    Thanks again!

    Best Regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Mastermind 21805 points

    Hello Cherry,

    Older devices like DRV8301 will not have this same behavior.

    Your second image shows noise on the nFAULT like or GND which is likely coming from somewhere else on the circuit.

    Thanks,

    Matt

  • 0 in reply to Matt Hein
    TI__Mastermind 22235 points

    Hi Matt,

    Thanks for your reply!

    The customer would like to know what is the difference between older devices like DRV8301 and the DRV8353 regarding the part of the circuit.

    From the figure above(I mean the second picture of the original post),  the waveform has affected the function. Interference issues can be filtered out by external capacitors or software, but they will cause delay in transmission of falling edge at fault.

    May I know the possible reason for that and how to solve the problem?

    Please help check it. Thanks a lot.

    Best Regards,

    Cherry Zhou

  • 0 in reply to Cherry Zhou
    TI__Mastermind 21805 points

    Hello Cherry,

    Older devices do not have this feature while new devices do have this feature. In newer devices the nFAULT pin is held low while the the power-up state machine is executing and the nFAULT pin is released once the power-up state machine completes. Older devices do not affect the nFAULT pin during the power-up sequence.

    Our customers typically use this to determine when the DRV has powered ON, and the rising edge on nFAULT indicates when the part is ready to receive commands.

    In older devices, customers had to wait for the maximum possible duration of tWAKE before sending commands because there was no clear way to tell once the device start-up was completed.

    A software filter is the ideal method to deal with this behavior, since you can very quickly ignore the first nFAULT low pulse when the device is powering up due to ENABLE or power on.

    Thanks,

    Matt