DRV8711: A&B PreDriver faults only with pulse to pin10 STEP, SPI step OK

Hi Dave,

Thank you for posting to the forum. Please give be 24 hours to research your question.

Thank you Pablo.  Your expert help appreciated, as this one has me stumped.

Hi Dave,

I have a few questions. They only thing that change is the method at which STEP is toggled (via SPI registers and hardware). Is this correct?

Dave Ercegovic said:

I am at a loss to understand why SPI commanded steps work fine, and hardware pulse command trips PDF.  Pulse input is opto isolated.

I am also not sure why this would happen. Will need to investigate this more. Maybe by going to the lab and testing it on the EVM. Did you capture any waveforms that you can share with me?

Pablo Armet said:

They only thing that change is the method at which STEP is toggled (via SPI registers and hardware). Is this correct?

Yes, that is correct.  All connections were the same.  The laptop stayed connected to the micro that communicates with the DRV8711  via SPI, and the signal generator stayed connected to the opto.  I could pulse OK by sending command to the micro via RS232 from laptop.  Then did a single pulse from signal generator and boom both A&B PDF.  Power cycled, and did single pulse via signal generator and boom both A&B PDF.  Always repeatable.

Pablo Armet said:

Did you capture any waveforms that you can share with me?

Let me work on that.  I presume you are after the 4 gates on the lower FETs, triggered by Pin 18 FAULT.

All the best,

Dave

Dave,

Thank you for answering the questions. Please send the waveforms when you collect them.

Pablo, am respecting your time as best I can.  I want to exhaust my trouble shooting capability.  I think I have found an anomaly in the data sheet section 7.6.5 BLANK Register:

The Blank register is described as:

Sets current trip blanking time, in increments of 20 ns
0x00h: 1.00 μs
…
0x32h: 1.00 μs

Should 0x00h be 0.00 us or is all values between 0x00h and 0x32h 1.00 us?

Clarification apprecitated.  All the best, Dave

Hi Dave,

Thank you for the information. I'm still reviewing your information so please give me a few more hours. Thank you in advance for your patience.

Not a problem Pablo.  Looking forward to the data sheet clarification.  I am working on some higher resolution scope traces... When the PDF triggers I am seeing very near or over 1.0 Volts on the gates of the Lower FETs.  Am dithering the drive currents to minimize.  I already have 47 Ohm resistors on the lower FETs, am going to respin the board and add 33 Ohms on the Hi FETs.

Hi Dave,

Regarding the datasheet clarification:

Dave Ercegovic said:

Should 0x00h be 0.00 us or is all values between 0x00h and 0x32h 1.00 us?

The blanking time between 0x00h and 0x32h is 1µs. Usually the output current can be very unstable when the FET is first enabled/disabled so during the blanking time, current measurements are ignored until the current has stabilized. Therefore, the blanking time cannot be 0s.

Dave Ercegovic said:

am working on some higher resolution scope traces... When the PDF triggers I am seeing very near or over 1.0 Volts on the gates of the Lower FETs

Is this voltage taken at the xxLS pins? Do you see this 1V voltage when using both the registers and external STEP pin to move to next indexer step? 

Dave Ercegovic said:

I already have 47 Ohm resistors on the lower FETs, am going to respin the board and add 33 Ohms on the Hi FETs.

Why do you want to reduce the gate resistance? is it reduce the rise time at the output voltage? if that's the case, you don't need to reduce the gate resistance. You can adjust the IDRIVEN/P to decrease the rise/fall time. I suggest testing at various drive currents.

Thank you again Pablo for the data sheet clarification.  I hope the powers that be will revise the data sheet in this area.  I have seen others confused on the blanking time register.

Here is the current configuration:

ctrl     = 0xE08; 
torq   = 0x15D; 
off     = 0x064;
blank = 0x032; 
decay = 0x110; 
stall    = 0xF01;
drive   = 0xFF9;

There are 47 ohm resistors between A1LS, A2LS, B1LS & B2LS and their respective FET gates
There are  0 ohm resistors between  A1HS, A2HS, B1HS & B2HS and their respective FET gates

Now with more testing, triggering with an SPI write to the RSTEP bit (CTRL register bit 2) OR triggering via the STEP pin (pin 10) are producing essentially the same FAULT of PDF.  I can send 100 SPI writes successfully, but I can get it to FAULT with an SPI write to RSTEP now.  I can now also get it to step 30 to 50 steps via the optically isolated STEP pin.

I am running a nominal 20 Vdc as Vm.  I am regulating around 1 amp phase current to the stepper.  I am using IRF4110 FETs with a total gate charge around 150nC.

I now have a hundred or so scope traces captured.  To me, every one is showing a gate voltage on either A1LS, A2LS, B1LS & B2LS ABOVE 1 volt at 2.2uS after start of transition.  I have documented the entire matrix of IDRIVEN (100mA, 200mA, 300mA, 400mA) and IDRIVEP (50mA, 100mA 150mA, 200mA) and all combinations trigger the PDF fault.  

I am attaching two annotated scope traces below

I thought I would look at both sides of the 47 ohm resistor on A1LS.  I found this interesting as there is about a 400nS period right after switching where it appears the DRV8711 has a very low Z to GND.  I have checked and rechecked the drive register and I have TDRIVEN and TDRIVEP both set for 2 uS.

To me it now looks like an excursion above 1 V at the 2.2uS mark.  Are the FETs I am using just not compatible with the architecture of the DRV8711 with 150nC total gate charge?

All the best,

Dave

Hi Dave,

Thank you for providing the plots and information.

Dave Ercegovic said:

There are 47 ohm resistors between A1LS, A2LS, B1LS & B2LS and their respective FET gates
There are  0 ohm resistors between  A1HS, A2HS, B1HS & B2HS and their respective FET gate

May I ask why you use gate resistors for LS FETs and not HS FETs. This will cause a mismatch on the output voltage slew rate even if same IDRIVEN and IDRIVEP are chosen. Can you remove 47ohm resistor and replace with 0ohm. See if that helps.

Dave Ercegovic said:

Now with more testing, triggering with an SPI write to the RSTEP bit (CTRL register bit 2) OR triggering via the STEP pin (pin 10) are producing essentially the same FAULT of PDF.  I can send 100 SPI writes successfully, but I can get it to FAULT with an SPI write to RSTEP now.  I can now also get it to step 30 to 50 steps via the optically isolated STEP pin

Interesting. The only setting you changed was the stepping rate (to half-step) and the stalln and BEMF settings. I don't think the BEMF is affecting the PDF faults. Somehow increasing the stepping rate is making the PDF faults occur when controlling via SPI. I'll need to look into this to really understand what is happening.

Dave Ercegovic said:

I now have a hundred or so scope traces captured.  To me, every one is showing a gate voltage on either A1LS, A2LS, B1LS & B2LS ABOVE 1 volt at 2.2uS after start of transition.  I have documented the entire matrix of IDRIVEN (100mA, 200mA, 300mA, 400mA) and IDRIVEP (50mA, 100mA 150mA, 200mA) and all combinations trigger the PDF fault.  

I think the 47ohm series resistor is limiting the IDRIVE current too much and not allowing the gate voltage to increase to its final value. As I suggested above, please remove the resistor or short it. This should allow the gate voltage to increase to it's final value.

Dave Ercegovic said:

To me it now looks like an excursion above 1 V at the 2.2uS mark.  Are the FETs I am using just not compatible with the architecture of the DRV8711 with 150nC total gate charge?

Did you follow the recommendations in section 8.2.2.3 of the datasheet? Please double check the Qg of your FETs meets equation (9) based on the settings you've chosen.