DRV3245Q-Q1: DRV3245 CRC8 calculation result

Daesik,

Do you have a TI representative that you have been working with?

I have an app note that should help with this but I think we need a safety NDA to share it.

Regards,

-Adam

dear Adam Sidelsky

i have done CRC8 calculation on 0x5102(IC control 0)

so, i'd like to comfirm result value to you that it is correct.

CRC8 calculation result value is 0x49

May i ask to confirm that the calculation result is correct?

Hi Daesik,

Adam will get you a response shortly. 

Thanks,
Aaron

Dear Adam Sidelsky

Let me ask you a little more detailed question

1. If you see the comments in CFG_CRC(1), it says to exclude RSVD. Then when all bits of 0x06 addr(LS Gate Driver Control register) are written as 1, the register value is 0b 0 0110 111 00 11 00 11 (0x3733).

If you say to exclude RSVD when performin gCRC calculation, does 0b 0110 111 00 11 00 11 become 0b0 0110 111 11 11? or will it be 0b0 0110 111 11 11 00 00?

If expressed in hexadecimal, does 0x3733 become 0x037F? will it be 0x37F0? I wonder.

2. I am trying to do a CRC System Implementation. 0xFF is entered in the first 8-bit CRC in, and MSB 8 bits (8-bit Command) of the 16-bit frame is entered in the 8-bit data In to perform operation. I wonder if it is correct to use the following calculation technique for this operation.The assumption will be made assuming that 0x037F in hexadecimal is 0x037F except for RSVD in the above question.

first 8bit CRC in : 0xFF

first 16bit frame : 0x037F

poly : 100101111

1111 1111                <- 0xFF : first 8bit CRC in

0000 0011               <- 0x03 : MSB 8bits(8bit command )

1111 1100 0000 0000

1001 0111 1    poly

0110 1011 10

  100 1011 11    poly

right????

3. I know that operation is done by sending 7 frames, and sending WRSPI and RDSPI. Then, when performing 7 consecutive CRC operations, if the read register and 0x01~0x04 registers also belong to 7 frames, are they subject to CRC operation?

Daesik,

I need to check the latest set of questions with the team and I will get back to you tomorrow.

Regards.

-Adam

Dear Adam Sidelsky

i wonder when can i get reply about my question

thanks

Daesik,

Did you get a chance to read the CRC app note I sent you?

I think there is some confusion. Based on question (1) above, it sounds like you are combining the CFG_CRC and the SPI read/write CRC. These are two separate mechanisms. The CFG_CRC check is designed to make sure that the data stored in the DRV internal register map does not get erased or corrupted. The datasheet discusses this in section 7.3.7.11. The other CRC is the SPI communication CRC which is used on all incoming and outgoing SPI communications to ensure there is no corruption in the SPI commands to and from the DRV. The datasheet discusses this in section 7.3.7.12.

Your explanation in question (2) looks correct.

I don't fully understand question (3) unfortunately if you could explain differently.

Regards,

-Adam

Dear Adam Sidelsky

Q3. When performing CRC8 calculation, read spi or write spi to CRC calculation without excluding specific bits and specific registers?

I try to perform CRC operation every 7 frames.

thanks

Daesik,

I think it would be best to have a short call to align on this. I am out of office next week for Thanksgiving in the US but can we meet the week of the Monday November 29th?

Regards,

-Adam