DRV3245Q-Q1: DRV3245CQPHPRQ1

Hi Zhi, 

The DRV3245-Q1 device uses a two-stage charge pump like mentioned. Here's some details below to explain the behavior:

Also, do you have access to the product datasheet?

1. The charge pump circuit relates to the main power supply voltage (PVDD)
   • when the PVDD is too low, it has to operate in 'tripler mode' to achieve the needed gate-drive voltage for the high-side pre-driver 
   • when the PVDD is sufficiently high, it will transition to the other stage: 'doubler mode' and it will be able to achieve the needed gate-drive voltage 
   • see description section below, from page22 of the datasheet. 
     
     
2. The charge pump current capability also varies with the PVDD voltage you are operating it at
   • please see section 'PREDRIVER Power Supplies' section of electrical char table (page10, I think) 

For your comment about driving the additional 3 MOSFETs for motor phase isolation, are you going to be driving them through some external circuit connected to the gate-drive signals: GHx, GLx, SHx, etc?

• if so, then that should be ok to try out if you are careful to avoid drawing too much current from the charge pump 
• the charge pump has some range of current output capability like mentioned above in point #2, so if you draw too much current it will pull down the charge pump voltage and trigger charge pump UVLO (undervoltage lockout) 

Thanks and Best Regards,
Andrew 

Hi Zhi,

I think for this DRV3245-Q1 device, there is no bootstrap diode (since it uses a charge-pump architecture instead to produce the needed gate-driver voltage for HS pre-driver) 

The datasheet section you shared (9.2.2.1 External MOSFET Support) is the correct guideline for calculating the MOSFET switching capability under 'average' gate drive current conditions like mentioned. 

• I think usually the inrush current is not usually a big concern for charge pump capability calculations, since the charge pump current capability spec is also rated for continuous dc currents
• In the case of inrush/peak currents of MOSFET switching, this only occurs for a brief period of the switching cycle and should not have a significant enough impact on your charge pump to cause a major dip in voltage 
  • the more important thing about peak gate drive current is to make sure that you select a proper IDRIVE setting for your MOSFET Qgd spec and desired rise time and fall time 
  • the impact of this will be to reduce transients observed on your MOSFET switch node (SHx) and Gnd 
  • if this does become a concern for your system, the mitigation plan would be to make sure you use a high enough PVDD voltage operating condition, since the charge pump current capability gets weaker as you lower your PVDD voltage. Using the highest PVDD setting will give you up to 30mA dc charge pump capability, giving the best chances to avoid VCP UVLO if your system's gate drive current needs are aggressively high 
• Attached some resources on this to explain further if interested:
  
  
  • Smart Gate Drive app note (https://www.ti.com/lit/an/slva714d/slva714d.pdf)

Also, one more comment regarding the equation for average charge pump current capability:

• the equation below expects only 6 MOSFETs of the same Qgd spec
• so if you are using another 3 external MOSFETs for phase isolation, 
• the equation will look more like: ICP_GATE > (6x Qgd + fPWM) + (current draw of your phase isolation MOSFETs) 
  • the additional phase isolation MOSFET current draw should be low, I think, since I am not expecting them to be switching often) 

Thanks and Best Regards,
Andrew