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DRV3205-Q1: Functions of register for SPI

Part Number: DRV3205-Q1

Hi Team, 

My customer have some questions for DRV3205-Q1, could you kindly help? Thanks.

1. Is there any material showing the detail how to set for SPI communication? 

2. Is there any material showing what each register exactly means(works for) to set SPI communication?  

BTW, I got this part number "DRV3205AQPHPRQ1-A" from customer but I can't find it on TI.com now, is it not available now? 

Thanks.

Regards,

Jo

  • Hi Jo, 

    Thanks for posting your question to e2e - please give us some time to investigate this further

    Responses may be delayed a bit due to the team being out during holiday timeframe.

    As a preliminary answer, 

    • the SPI communication guidelines are in the official product datasheet for DRV3205-Q1 
      • this info includes info like specific timing/frequency parameters and SPI frame command-word definitions, as well as SPI pin connections (nSCS, SDI, SDO, SCLK) 
    • you may need to gain access to the internal datasheet in order to view this information
      • may need to move this post to the MD Internal forum. Who is your customer, and do they have a Safety NDA signed with TI? 
      • once the SafetyNDA is released, then we can release the datasheet for viewing 

    As for the DRV3205A device, I think it's just a minor variant of the DRV3205-Q1 device, and may even be covered by the same datasheet.

    Will check with the team on this 

    Best Regards, 
    Andrew

  • Hi Jo, 

    Following up on this item - sent you an internal email message to discuss further. 

    The information in my previous response should be accurate for detailing the SPI settings in this DRV3205-Q1 device, 

    And any additional datasheet-specific information would need to sign an NDA first before we can share that publicly 

    Best Regards, 
    Andrew