Other Parts Discussed in Thread: DRV832X, DRV8328
Hi Experts!
When I trigger an oscilloscope on one of the PWM inputs to the DRV8343, I see approximately 45 nanoseconds of jitter on the corresponding gate drive output.
Section 8.3.1.4.3 Propagation Delay of the data sheet mentions several small delays which makes sense to me but I am wondering what "small" means and if it is possible for these delays to produce this amount of jitter. The jitter seen when the gate turns on and when it turns off appear to be uncorrelated. I may have been wrong in thinking that independent mosfet mode put the chip into a fairly direct drive mode. That is, the smart gate drive features were mostly bypassed such that there would be a relatively fixed timing between the PWM input and the gate drive outputs.
So, several questions arise:
What internal logic remains in the signal path in independent mosfet mode that we would need to consider?
Is it possible for this logic to produce a 45 nanosecond jitter or variation?
Since we have set a deadtime close to this variation, does the chip design guarantee that the variation cannot produce a shoot-through condition?
Thank you,
Cameron