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Original question:

DRV8803: Logic status after reset

DRV8803: DRV8803 nENBL and RESET status

Zoe Yang
Intellectual 2210 points
Part Number: DRV8803

Hi experts,

When my customer using DRV8803 as PLC DO driver.There are some questions I would like your comments for deeply explain our datasheet features.

  • Q1:In below nENBL and RESET features, what is the difference between nENBL and RESET? Can I think of RESET low is normally transport signal from in to out?

Pin

I/O:High (1)

I/O:Low(0)

nENBL

Disable output drivers

Enable output drivers

RESET

Reset internal logic(Input ignored)

Normally input?
  • Q2: What does RESET active high actually mean? Do we active RESET internal logic by switch off Nmosfet internally? Or any other ways?
  • Q3:What is the port status of the input if RESET set active high?  It has internal pulldown resistor does it mean reset the I/O status to 0?
  • Q4:In below features we mentioned Vclamp has two ways of connection. But can we float the Vclamp instead? What is the consequence if float Vclamp?  Customer has another power supply to connect VM. They don’t want to connect VClamp to VM.

 

I am looking forward to your reply and have a good day! Thank you!

  • 0
    TI__Guru 55605 points

    Zoe,

    1) RESET is used to clear faults and reset digital core.  nENBL just controls whether the output transistors are enabled or not.  Yes, you can think when RESET = LOW that inputs are passed normally to outputs.

    2)  Similar answer to #1.  Think about it as a reset on a MCU.  When you cycle RESET, all faults are cleared.  It is mainly meant for this operation.

    3)  When device is in RESET state (HIGH), all inputs are ignored.  That is all.

    4)  Can you draw the circuit the customer wants to use?  We do NOT recommend leaving VCLAMP unconnected.

    Regards,

    Ryan