DRV2511-Q1: Design issue

Hi Cherry

Cherry Zhou said:

Q1: What is the purpose of a loop that requires an additional LPF on the PWM control loop? In a design, what is the principle if the filter capacitance of PWM+ is removed and it is prone to pull the INTZ low (overcurrent protection) causing the drive IC to not operate?

The LPF at the IN+/IN- Pins is intended to filter the PWM signal into a smooth analog signal. The DRV2511 is an analog input amplifier. the LPF in the design is necessary if you want to use a single pin (that is not a DAC) to drive the amplifier with PWM. As you mentioned, the steep PWM edges can draw too much current causing OCP to be flagged.

Cherry Zhou said:

Q2: In the case of single-ended inputs, the INB is handled in three ways, what are the differences and how to choose them?

If the input is tied to GND, then the amplifier will be operating in a non-linear region, this will cause a slight increase in THD. Using a voltage divider, or a cap to GND will have better THD performance. Since a Cap to GND uses less passive components the capacitor method is recommended.

Cherry Zhou said:

Q3: When the power supply is powered up, the IC itself generates a PWM pulse of 10 ms. Why is that?

Where is this pulse being seen? is this at the OUT+/OUT- pins of the amplifier? is there a similar pulse at the input pins?

Regards,

Arthur

Hi Arthur,

Thanks for your help here.

Arthur Brown said:

The LPF at the IN+/IN- Pins is intended to filter the PWM signal into a smooth analog signal. The DRV2511 is an analog input amplifier. the LPF in the design is necessary if you want to use a single pin (that is not a DAC) to drive the amplifier with PWM. As you mentioned, the steep PWM edges can draw too much current causing OCP to be flagged.

When no capacitance is added, the waveform is a normal square wave. Why does this cause the OCP to be flagged? What is the OCP tagged standard? Is it labeled as soon as 13 A is reached?

Arthur Brown said:

If the input is tied to GND, then the amplifier will be operating in a non-linear region, this will cause a slight increase in THD. Using a voltage divider, or a cap to GND will have better THD performance. Since a Cap to GND uses less passive components the capacitor method is recommended.

They have attempted to use a capacitor to ground when designing, but it could result in excessive current and significantly increased back-end vibration. What is the reason for that?

Arthur Brown said:

Where is this pulse being seen? is this at the OUT+/OUT- pins of the amplifier? is there a similar pulse at the input pins?

It is being seen at the PWM+ pin of the IC. Out+ will have a short pulse (up to around 30 V) during a change from 0 to 6 V, as above Q4.

Thanks and regards,

Cherry

Hi Cherry,

Cherry Zhou said:

When no capacitance is added, the waveform is a normal square wave. Why does this cause the OCP to be flagged? What is the OCP tagged standard? Is it labeled as soon as 13 A is reached?

the OCP should only trip once the 13A limit is reached. If the flag is being set I suspect that it is truly because this limit is reached

Cherry Zhou said:

They have attempted to use a capacitor to ground when designing, but it could result in excessive current and significantly increased back-end vibration. What is the reason for that?

Can you explain more what you mean by "back end vibration" and "significant current". is there a DC current through the load?

Cherry Zhou said:

It is being seen at the PWM+ pin of the IC. Out+ will have a short pulse (up to around 30 V) during a change from 0 to 6 V, as above Q4.

I wouldn't expect that the input pins of this IC are able to drive 6V, If R711 is removed is the pulse still seen?

Regards,

Arthur

Hi Arthur,

Thanks.

Arthur Brown said:

Can you explain more what you mean by "back end vibration" and "significant current". is there a DC current through the load?

The load is a vibrating module (mainly composed of a large coil), and when the filter capacitance of PWM+ is removed, the vibration intensity becomes significantly larger.

This pulse is still present after the R711 is removed.

Also, what causes the pulses at the output and How to filter out? When testing the output, the inductor front end out+/out- will be offset (i.e., there will be a glitch when out+ - out-, as shown in the following figure)

Thanks and regards,

Cherry

Hi Cherry,

I apologize I did not get a chance to review your response today. I will take a deeper look at this tomorrow and post back.

Regards,
Arthur

Hi Arthur,

Understood and thanks for your help again.

Regards,

Cherry

Hi Cherry, 

I understand that this pulse is generated by the DRV itself. I searched around E2E and found some other threads mentioning the same phenomenon. I will test this in the Lab and see if I can see the same

Regards,

Arthur

Hi Arthur,

This is Jiawei, the question Cherry asked is from my customer, do you have any update on Q3 and Q4?

Q3: When the power supply is powered up, the IC itself generates a PWM pulse of 10 ms. Why is that?

Q4: When out+ rises from 0 V to 6 V during power up, a pulse is generated, why is this pulse generated? How is this pulse filtered out?

Thanks！

Jiawei

Hi Jiawei,

Arthur is out of office for the next 2 days. He will get back to you when he returns.

Regards,

Jeff

Hi Jeff,

Any further update here, thanks!

Q3: When the power supply is powered up, the IC itself generates a PWM pulse of 10 ms. Why is that?

Q4: When out+ rises from 0 V to 6 V during power up, a pulse is generated, why is this pulse generated? How is this pulse filtered out?

BR

Jiawei

Hi Jiawei,

I apologize for the delay here. I will replicate the issue in the lab and look for a way to filter this pulse. I will post back on Friday

Regards,

Arthur

Hi Arthur,

Could you kindly give some update here?

BR

Jiawei

Hi Jiawei,

Arthur has been catching up after some time out of office. He will get back to you tomorrow.

Thank you for your patience,

Jeff

Hi Jeff,

Customer are urgent for this, could you kindly give me some feedback tomorrow? Thanks!

BR

Jiawei

Hi Jiawei,

I will make this my first priority once I am in the office tomorrow (in about 12 Hrs) I tested this briefly, and was able to recreate a small pulse at the output. I will do some more testing tomorrow and provide recommendations/explanation

Regards,

Arthur

HI Jiawei,

I was able to replicate the same pulse behavior on an EVM.

There will be a pulse at IN+/- when the  device is enabled with the EN pin.

I was able to remove this pulse if I power the device with EN = Low.

When I power the device with EN = High and STDBY = Low. I see there is also a differential pulse on the outputs

To remove this pulse 

1) power the device with EN = Low and STDBY = High

To Play a vibration

2)Enable the device by setting  EN = High and STDBY = High

3) Play a waveform to the IN+ pin with EN = High and STDBY = High

4) Set EN = High and STDBY = Low. This will allow the vibration to be felt

Also, please as the customer to check the resistance of IN+/IN- to GND, and the resistance of  OUTP/OUTN to GND and each other.

I want to make sure that there is no short causing the OC detection to be tripped.

Regards,

Arthur 

Hi Arthur,

See below feedback pls. Another question is that the inductance  will heating when the output has no load, could you kindly tell me the reason? Tanks!

PWM+           1.9kΩ

PWM-           0（0Ω电阻接地）

Out+             285kΩ

Out-             285.3kΩ

BR

Jiawei

Hi Jiawei,

Do you mean that when there is no load connected and no waveform being played inductor L703 and 704 heat up?

if the device is active the Idle state of  OUTP/OUTN will be a 50% duty cycle square wave. This will be in phase between both the outputs, but the current to charge/discharge capacitor C723,724  may be the cause of this heating.

Can the customer take scope shots of the OUTP OUTN terminals during the Inductor heating condition?

Regards,

Arthur