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DRV8323: Schematic Questions

Part Number: DRV8323
Other Parts Discussed in Thread: CSD88599Q5DC, , TIDA-010072

Hi, we have a couple of schematic questions

Our application:
DRV8323S with CSD88599Q5DC MOSFET
VM = 18-24V
Motor phase currents: 10 A max RMS, 15 A max peak

Questions:

- Given the above application, would you recommend any series resistors on the gate driving pins of the DRV8323? Are there any IDRIVE settings which could result in problems?

- If calibration is done over SPI, is there any difference whether CAL is floating or tied to GND considering it has an internal 100k PD

- We are planning on adding a LPF on the SOX pins of the CSA. What would be a recommended cut-off frequency?

- Given that we have a LPF on the output of the CSA, is any filtering required on the CSA diff inputs? For example, the datasheet recommends 1000 pF across the inputs (which matches our design) but the TIDA-010072 reference design also includes 10R series resistors. Please advise

Thanks

  • Hi Daniel,

    Thanks for your questions! Regarding your first question, it is a good idea to include gate resistors to start with just in case you need to fine tune the IDRIVE strength in between 2 settings. Because of the Qgd of the MOSFETs that you are using (7nF), I would recommend using no higher of a gate drive current than 60mA/120mA source/sink, and if you use that high of an IDRIVE setting you will likely need to add some small value gate resistors to slow down the gate current a little bit to avoid too much ringing on the gates and sources of the MOSFETs during switching. Depending on your layout the 30mA/60mA IDRIVE setting should work fine without gate resistors to achieve a MOSFET slew rate of approximately 235ns/116ns rise/fall time. If you feel that you want to achieve a faster switching time, you could switch to the 60mA/120mA IDRIVE settings but as I mentioned before you will want to have gate resistors to help slow down the switching time with that IDRIVE setting to avoid excessive ringing that could cause damage. Most customers consider 200ns/100ns rise/fall time to be fast, and PCB inductance in the gate and source paths can lead to parasitic ringing that could present issues at faster switching speed.

    If calibration is done over SPI, I don't see any issue with leaving the CAL pin floating since it has an internal pulldown, as long as there is no noise that could couple into that pin that could cause it to go above a logic low voltage. 

    I will look more into your last 2 questions and try to get a response to you in the next couple days. 

    Regards,

    Anthony Lodi

  • Hi Daniel,

    To answer your last 2 questions:

    1. On our DRV8323Rx EVMs we used an R= 56 ohm, C = 2200pF low pass filter on the CSA outputs to achieve a cutoff frequency of about 1.3MHz. I would recommend starting with that and then adjusting the values if necessary during validation of the board if you feel a different cutoff frequency works better for your application.

    2. Adding series resistors on the inputs of the CSAs is not a requirement, but they can help create a low pass filter with the capacitor to filter out higher frequency noise that could be present on the inputs, especially when higher currents are present and if there is parasitic inductance in the current path. I don't see series resistors implemented in a lot of customers designs, but there are instances where customers choose to do so. Your application is more of a medium current level design, you may decide to have the series resistance footprint available on the inputs to the CSAs and just populate them with 0 ohm resistors to start with so that you can go back and add in a small resistance value to create a low pass filter if you feel that ringing on the inputs of the CSAs are an issue during testing and validation of the PCB. 

    Regards,

    Anthony Lodi

  • Thanks Anthony, I will address each of these below

    1) Is there a reason why the EVM did not do it? We are using the same FETs and have a similar layout and want to avoid using any unnecessary components on switching nodes considering they add inductance

    2) Will ground pin

    3) Understood - we will do something similar

    4) Would the LPF filter on the output not also address this noise? We want to avoid adding redundant filters and taking up space in our board layout unless needed

  • Hi Daniel,

    1) Adding the gate resistors is really a matter of design considerations: It gives an added layer of granularity when it comes to MOSFET switching time vs EMI concerns. Using the 30mA/60mA IDRIVE setting without gate resistors should work fine with the MOSFETs you are using, but you may feel that you would like to achieve a faster MOSFET switching time for your particular application, so you may decide to increase the IDRIVE setting to 60mA/120mA. If you do, you may find that using the 60mA/120mA setting results in EMI issues/ringing that could be problematic due to the very fast switching times. In order to achieve faster switching times than with the lowest IDRIVE setting, but to reduce the ringing issues that are a result of using the 60mA/120mA setting, you may decide you want to use a small gate resistor to slow down the gate current a little bit while using the 60mA/120mA IDRIVE setting. Although we didn't include gate resistors in the EVM, it is one thing that can be added to provide a little more fine tuning to fit particular design requirements if desired. 

    4) The LP filter on the CSA outputs will help in mitigating the noise, so you may decide you don't think input filtering with the series resistors will add enough value to justify the extra board space. However, input filtering will aid in adding another layer of filtering to filter out some of that noise before it even goes into (and is amplified by) the CSAs. I don't think it will be necessary to have the input series resistors especially if the layout is optimal, but it would likely improve noise filtering even more if you decided to include them. 

    Regards,

    Anthony Lodi