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DRV8706-Q1: Off-line diagnostics - how they work & how to use them

Ian Wylie
Prodigy 40 points
Part Number: DRV8706-Q1

Hi - I'm trying to understand the DRV8706S-Q1 off-line short-circuit & open load diagnostics and how to use them properly.

I've looked at the datasheet and available literature (Open Load Detection in Motor Drivers - slvae49a, Detecting Short to Battery and Ground Conditions with TI Motor Gate Drivers - slvaev8) but I find these are quite vague and they don't really cover the off-line case very well or at all.  Is there is any other documentation anywhere that might have further explanation or any usage examples?

Looking at the datasheet section 7.3.8.11 and figure 7-20, it looks like once the outputs are disabled and the OLSC_EN bit is enabled I can then enable the PU_SHx/PD_SHx bits to enable the four current sources in turn to generate a voltage across the Vds comparators that could be affected by the external FETs and load.  The four Vds comparators monitor the drain-source voltages and control the VDS_H/L1/2 bits in the VGS_VDS_STAT register accordingly.

Are the current sources are powered from the DRAIN pin/H-bridge FET supply (so we need this to be active), or from an internal supply source?

Can I also assume that the series diode and current source shown in figure 7-20 generates a higher diagnostic voltage drop than in normal operation across the inputs of the Vds comparators?
I assume that this explains the statement in section 2 of Open Load Detection in Motor Drivers - slvae49a where it says: "BDC gate driver passive OLD recommends the VDS comparator thresholds should be adjusted to 1-V or greater to ensure enough headroom for the internal blocking diode forward voltage drop".

If this is the case, then I'm not sure how the comparators detect the faults: If the Vds OCP threshold is set to (say) 1.4V or 2V to be above the diagnostic voltage, then if there is no fault the Vds drop will not change, if there is a short in the FET for the enabled current source the Vds will drop to 0V (again no change), but if there is a fault to DRAIN or GND then a comparator somewhere should trip?

So, for example, if I enable PU_SH1 the driver will generate a voltage across FET H1 and a voltage at the SH1 and SH2 pins, although I'm not sure where the current from the source goes (comparator inputs?).
I'm assuming that the L1 and L2 FETs won't pass this current if they are operating correctly because the channel is off and their body diodes are reverse-biased, and the H1 & H2 FETs also won't pass this current because they are off and their body diodes are also reverse-biased as the DRAIN pin voltage > SH1/2 pin voltages.

As an example fault scenario let's say (when PU_SH1 is enabled) that FET H1 is short (or there is a short to DRAIN from SH1): SH1 and SH2 will both rise to the DRAIN voltage, the H1 (and probably also the H2) FET Vds comparator will not indicate any change as it's diagnostic threshold will not have been crossed, but the L1 & L2 Vds comparators will see a change as their thresholds will be crossed?

I'm still trying to work this through, but I don't think that I have enough detail about how the off-line diagnostics work or how to use them so any help would be appreciated.

Thanks

  • 0
    TI__Mastermind 44605 points

    Hi,

    Thank you for question. We will review and reply within 24 hours.

    regards

    Shinya Morita

  • +1 in reply to Shinya Morita
    TI__Mastermind 44605 points

    Hi,

    Let me add my comment here.

    Looking at the datasheet section 7.3.8.11 and figure 7-20, it looks like once the outputs are disabled and the OLSC_EN bit is enabled I can then enable the PU_SHx/PD_SHx bits to enable the four current sources in turn to generate a voltage across the Vds comparators that could be affected by the external FETs and load.  The four Vds comparators monitor the drain-source voltages and control the VDS_H/L1/2 bits in the VGS_VDS_STAT register accordingly.

    SM: Yes, this is correct understanding. Offline means Output is OFF- let's say external FETs are OFF.

    Are the current sources are powered from the DRAIN pin/H-bridge FET supply (so we need this to be active), or from an internal supply source?
    SM: For Offline diagnostics, PVDD, DRAIN, DVDD should be supplied. Without those supply for DRV, offline diagnostics does not  work.

    For OPEN, GND etc fault case use example, please refer attached slide. 

    Thanks,

    regards

    Shinya Morita

    4810.DRV87xx-Q1_Offline_OL_SC.pdf

  • 0 in reply to Shinya Morita
    Prodigy 40 points

    Hi Shinya,

    thanks for the notes and slides.  This is starting to explain but I have some more questions.

    In all example cases the same PU_SHx and PD_SHy are enabled - I assume that this is done to provide a current path as shown by the green arrows, is a PU+PD "top-to-bottom" current path always required to allow test currents to flow?

    For the no fault case, how do the SHx and SHy nodes arrive at PVDD/2?
    I can see that if this is the case then all comparators will read as '1' with PVDD/2 across them.

    For the open load fault case, I can see that if the load is disconnected then the current flow will be interrupted, but why is the SHy node then assumed to be at GND  instead of floating?  Is there some kind of internal bias or pull?
    I can see why the VDS_Ly reads as '0' if the SHy node is really grounded, and why the VDS_Hx reads '0' as there is no voltage drop across the VDS comparator.

    I assume that the enabled current source pair could be swapped PU_SHy/PD_SHx) to cover other fault cases depending on (for example) where an open load disconnection has occurred (e.g. at the SHx pin)?

    Thanks,
    Ian

  • 0 in reply to Ian Wylie
    Prodigy 40 points

    I've done some more research on this subject, mainly by looking at the competition to see how other devices do these off-line diagnostics (for example, the Infineon TLE9560-3 which has an open-access app note on off-line diagnostics that anyone can download).

    The Infineon part has permanently-enabled pull-up current sources of ~4.5 times lower current than the pull-down current sources; this allows the pull-down sources to essentially ground the source pins when enabled, in the DRV8706 the pull-up/down currents are the same which I now believe is why the SHx/y pins settle at PVDD/2 when a pull-up and pull-down source are enabled and there is no fault.

    In the example slides, when there is an open-load fault and the pull-up current source PU_SHy is disabled I still can't see why the SHy pin goes to GND on the 'far' side of the disconnection (where the pull-down source PD_SHy is enabled) unless the pull-down current source acts like a low-value resistor under these conditions and effectively grounds the SH pin - is this a valid interpretation?

    Otherwise I think I now understand most of this function.

    Thanks,
    Ian

  • 0 in reply to Ian Wylie
    TI__Mastermind 37683 points

    Hi Ian,

    Shinya is out of the office today. He will provide a reply when he gets back. Thanks in advance for your patience.

  • 0 in reply to Pablo Armet
    Prodigy 40 points

    I think that after resurrecting my DRV8706S evaluation board and doing some experiments I'm now happy with my understanding of the off-line diagnostics.

    Thanks for your help,
    Ian