DRV8662: Drives two cascaded piezo ceramic

Hi Cherry,

Apologize for the delay I will give my response later this week

Regards,

Arthur

Hi Arthur,

Thanks and expect the response.

Thanks and regards,

Cherry

Hi Cherry,

Sorry for the delay here. I needed to order DRV8662 EVM in order to test this.

I will give my thoughtful response tomorrow

Regards,

Arthur

Thank you for the detailed explanation

I am the customer mentioned by Cherry.

"You cannot connect OUT- directly to GND. the piezo can be connected in series to achieve up to 50V DC across both, or then can be connected in parallel to achieve 100V across both."

1) Do you mean in the following connection, the piezo can be connected in series to achieve up to 50V DC across both?  Is this usage recommended? 2) Do you mean if I remove the red wire, then can be connected in parallel to achieve 100V across both? If I do not remove the red wire (which is exists in the products), they are in cascaded connection, not a parallel connect.

"No, you cannot connect OUT- to GND. In addition to this the voltage difference between PVDD and OUT+ will not be 100V. it will be close to 0V."

Now I disconnect OUT- with GND in the following figure. Do you mean the piezo will be applied close to 0V in this case? 

Hi Xiang,

I think that I misunderstood the actuator in my previous reply. You need to drive cascaded piezos with a DC voltage. and the voltage on the piezos can never be negative

1) Is my understanding correct?

2) will the voltage across the piezos (I am calling them A, and B) be the same? or will you need different voltages across them. for example 70V on A, and 90V on B?

When I said 50V in series or 100V in parallel this is what I mean;

If my understanding is correct then I do not think that DRV8662 is suitable to drive this actuator. the maximum DC voltage that can be generated by this part relative to GND is 105VDC. this part will not be able to drive 100V across two piezo in series because that would require a 200V to GND DC.

from your example;

If you need higher than 100VDC, you should consider https://www.ti.com/tool/DRV2700EVM-HV500 This reference design is able to achieve up to 500VDC, and it may be a possible solution in this case.

Regards,

Arthur

"You need to drive cascaded piezos with a DC voltage. and the voltage on the piezos can never be negative"  This is what I mean.

"will the voltage across the piezos (I am calling them A, and B) be the same? or will you need different voltages across them. for example 70V on A, and 90V on B?" Yes

I do not the hope to get 100V on A and 100V on B. I hope the sum of voltage on A and voltage on B is a constant 100V. For example 30V on A and 70V

on B.

Do you think the following connection can satisfy this need? Why? 

If the VBST has already established, assume the OUT+ is in a process of rising from 0V or 100V. In the meantime, the Piezo B is charging and the Piezo A is discharging. A will source current to VBST, Is this allowed?

Thank you. The question is well resolved.

I have further question.

" The boost output voltage may be programmed as high as 105V. A capacitor with a voltage rating of at least the
boost output voltage must be selected. Since ceramic capacitors tend to come in ratings of 100 V or 250 V, a
250 V rated 100 nF capacitor of the X5R or X7R type is recommended for the 105 V case. The selected
capacitor should have a minimum working capacitance of at least 50 nF"

C2 is 0.1uF normally. Is it large enough to decouple any voltage spike seen on VBST?

@Arthur Brown

Thank you

Thank you so much

Each piezo in the application is 0.8uF. Is 0.1uF sufficient?   The voltage  tolerance of the decouple capacitor should be 150 uF considering the boost voltage is 105V,  If I use 1uF capacitor, can I easily find a regular capacitor whose voltage tolerance meets this requirement?

I think there is a possibility that 0.1uF is sufficient, because in normal operation, when Piezo B is charging, Piezo A is discharging. the current discharges from Piezo A may flow to Piezo B though the DRV8662 from VBST pin? and when B is discharging and Piezo A is charging, the current discharges from Piezo B may flow to Piezo A though the DRV8662 from OUT+ pin? Is this guessing correct?

Hi,

I think that it is possible to find a 1uF capacitor with a voltage rating higher that 105V. I found a few by searching mouser.com

The DRV8662 shares the same boost architecture as DRV2700, and in the DRV2700 datasheet the gain bandwidth for 1uF load 105V VBST is ~40 Hz. I know that these plots where collected with 0.1uF boost capacitor. So for your application 0.1uF should be able to handle the current needed,

I think that your guess is correct, when piezo B charges and  A discharges, that charge will flow to VBST node and then through the device into Piezo B.

When Piezo B discharges I do not think the charge will flow through the device into piezo A. I assume, that it will be sent to GND and dissipated in the device as heat,

Regards,

Arthur

Thank you.

We reach a good agreement.