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MCT8316A: 100US inter-byte delay

Cherry Zhou
Mastermind 22235 points
Part Number: MCT8316A
Other Parts Discussed in Thread: TMS320F28388D

Hi team,

Here's an issue from the customer may need your help:

As the figure above, is the 100US delay between bytes necessary? What happens if this delay is not added?

The I2C peripheral of a general controller, such as TI's C2000 family of processors, typically sends data to the FIFO and the hardware completes the transmission, such an interbyte delay, it won't be so much easy.

Could you help check this case? Thanks.

Best Regards,

Cherry

  • 0
    TI__Mastermind 24415 points

    Cherry,

    This 100 us interbyte delay is required for the MCT8316A. Without this delay, you will see the device getting stuck and you will have to power cycle to restart the device.  This is an errata in MCT8316A and this will be fixed in the next version of the same device. 

    Regards,

    Vishnu

  • 0 in reply to Vishnu Balaraj
    TI__Mastermind 22235 points

    Hi Vishnu,

    Thanks for your help.

    Vishnu Balaraj said:
    you will see the device getting stuck

    First read the 8316A EEPROM to verify IIC communication, TMS320F28388D for MCU.

    First copy the EEPEOM contents to the shadow register and send the following instruction: 0x10 0x00 x0E6 0x40 0x00 0x00 0x00, 7 bytes total. The first three bytes are the control word (meaning this is a write), and the CRC is not enabled. The register to be written is the Algorithm Control Parameters REG at address E6 in RAM space. The last four bytes are the instruction contents, and since the manual does not point out whether reading RAM space registers is LSB Byte first or MSB Byte first, the customer has also tried writing 0x00 0x00 0x40.

    Regardless of what is written, each time the IIC sends these 7 bytes, the IIC receive Buffer receives them, and the 100US delay between the 7 bytes does not add.

    Dose this is a kind of situation of "getting stuck"?

    Also, when receiving 8316A of data, does SCL need to add 100US delay between bytes when the IIC bus is supplied by the master 28388D?

    Thanks and regards,

    Cherry

  • +1 in reply to Cherry Zhou
    TI__Mastermind 24415 points

    Cherry,

    The master should add the 100 us delay on SCL between bytes.

    Regards,

    Vishnu