MCF8316A: Questions regarding datasheet

Hideki-san,

Here's my response.

Hideki Hayashi1 said:

Regarding PWM input (7.3.8.2), it is 13 bit resolution when 1 kHz PWM is used. Does it means input duty is read with 8192 (2^13) steps, correct?

Yes, that's correct.

Hideki Hayashi1 said:

Is the output PWM resolution same as input PWM resolution (13 bit) ?

Output PWM resolution is not same as input PWM resolution. Resolution of output PWM depends on the PWM output frequency [PWM_FREQ_OUT]

Hideki Hayashi1 said:

Regarding FG_DIV (7.3.20.1), it is understood to set the ratio of electrical cycle vs mechanical cycle in order to set FG frequency. Is there other function refer FG_DIV such as the FOC algorithm?

I didn't quite understand your question. FG_DIV is used to set the electrical: mechanical cycle ratio.

Hideki Hayashi1 said:

Is the fig.7-45 just a illustration of divider? Or is it explaining FG output must sync with Phase voltage?

Purpose of showing this figure is to illustrate the FG pulses at different FG_DIV settings. Phase voltage of one of the phases will be in sync with FG.

Hideki Hayashi1 said:

Customer uses 12 slots / 8 poles motor. Can they configure as 12 pulse / mechanical 360 deg (3 pulse / electrical 360 degree)?

It is possible in MCF8316A to configure to 3 pulse/electrical degree. But it is possible to configure to 2 pulses per electrical degree. 

Hideki Hayashi1 said:

Regarding DC Bus Current Limit (7.3.21), Does it mean the device limits current when the DC bus current is over the set current, or the device draw DC bus current in regardless of PWM duty of the SPEED pin?

Device limits the current when the actual DC bus current is above the set current threshold.

Hideki Hayashi1 said:

Regarding AVDD Linear Voltage Regulator (7.3.4), how to deal with FB_BK pin in case internal buck regulator is not used and AVDD linear regulator is used, and the voltage source of LDO is connected VM?

It is always required to populate the external resistor/inductor and capacitor on FB_BK pin as recommended in the datasheet even if the buck is not used because this buck power is used internally in the IC to power up analog and digital blocks. . 

Regards,

Vishnu

Hideki Hayashi1 said:

Understood about the carrier frequency. What is the resolution of output PWM? I cannot find any description in 7.3.15, register map, electrical characteristics...

Output PWM frequency Fsw is not stored in any register. Output PWM frequency Fsw get updated every 1/Fsw seconds. 

Hideki Hayashi1 said:

What I wanted to ask is if there are any other effects other than electrical: mechanical cycle ratio.
Since FG is a motor speed feedback, I am checking to see if it could affect the operation of the FOC algorithm, for example.

FG is an output pin and it cannot affect the FOC operation in any way. I don't see any other effects other than the electrical and mechanical ratio. 

Hideki Hayashi1 said:

Sorry, it means both are possible? I am confused since you say 'but'.

I meant, it is NOT possible in MCF8316A to configure to 3 pulse/electrical degree. But it is possible to configure to 2 pulses per electrical degree. 

Hideki Hayashi1 said:

Internal LDO can be supplied from VM. Not only LDO, but also the buck is still needed for internal block, correct?

Yes, that's correct.

Set CLOSED_LOOP1 / FG_DIV[11:8] to 0h to output 2 pulses per electrical degree. 

Regards,

Vishnu