Other Parts Discussed in Thread: TMS320F28386S, DRV8302
Hi,
I am using the DRV8323RS.
I don't understand Gate Drive truth table that the driver is implementing.
See the truth Table I scoped.
INL | INH | GL | GH |
0 | 0 | 0 | 1 |
0 | 1 | 0 | 1 |
1 | 0 | 1 | 0 |
1 | 1 | 0 | 1 |
This looks like nothing on the data sheet.
See attached Scope capture.
The 6 bottom channels are the inputs.
The order from bottom to top is: INHa, INLa, INHb, INLb, INHc, INLc
The 6 top channels are the outputs in this order: OUTHa, OUTLa, OUTHb, OUTLb, OUTHc, OUTLc.
Also, I tried to update the PWM_MODE bits to 11b (independent mode)
I have written the correct value to the "Control Register" and also read back the value to make sure the value is actually set.
The Gate Drive acts exactly as described above. As if the device ignores the setting.