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DRV8889-Q1: VM and VCC timing requirement

Ann_Lien
Genius 10640 points
Part Number: DRV8889-Q1

Hello expert,

May I know if DRV8889-Q1 has requirement for VCC/VM timing sequence? Thanks a lot!

Best regards,

Ann Lien

  • 0
    TI__Guru 54675 points

    Ann,

    I am a little confused.  We don't have a pin called "VCC".  All regulators are internally generated from VM voltage.

    Can you help explain?

    Regards,

    Ryan

  • 0 in reply to Ryan Kehr
    TI__Genius 10640 points

    Hello Ryan,

    Sorry to be late. VCC should be VSDO and VREF. Thanks!

    Best regards,

    Ann Lien

  • 0 in reply to Ann_Lien
    TI__Guru 54675 points

    Ann,

    Got it...thank you for the additional explanation.

    There are no timing requirements necessarily between VM and VCC.

    However, VCC definitely should be stable before any SPI communication as this is the reference for the SDO output buffer.  Also, VCC should be stable before issuing any pulses on the STEP input as VCC is the reference for current regulation in the device.  

    And of course VM should be up before communication or stepping as VM is the source for all the internal regulators.  

    VM can be up first without VCC.  There is no reliability concerns for VM applied to the device BEFORE VCC.  This is OK.

    Regards,

    Ryan