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Phase shift of sample-and-hold

Bui Van Linh
Intellectual 660 points


Hello experts,

I already posted this question up yesterday. But I think I posted in the wrong forum.

At the moment I am reading the blog of Dave Wilson

https://e2e.ti.com/blogs_/b/industrial_strength/posts/teaching-your-pi-controller-to-behave-part-vi

I can't understand the diagram of phase shift of a sample-and-hold in this blog.

The phase shift is caused by the delay time and you can calculate it very easily (see picture)

With a normalized frequency of 0.1 I have a phase shift of -36 degrees and not -18 degrees as the blog says.
where is my calculation mistake?

Thanks in advance - Bui

  • 0
    TI__Guru 55665 points

    Bui,

    I am not sure what forum you posted to before, but I have alerted the industrial motor drive team to this post.

    Regards,

    Ryan

  • 0 in reply to Ryan Kehr
    TI__Expert 3580 points

    Hello Bui,

    I think Dave Wilson normalized to the maximum modulated PWM signal (Nyquist) and not the PWM carrier, where the maximum signal frequency
    is 0.5-times the PWM carrier frequency.

    Example: A 10kHz PWM carrier (100us updater) allows a maximum 5kHz frequency (Nyquist). The phase lag of a 10kHz PWM will 0.5-times the PWM
    carrier = 50us. This equals 90 degree with respect to the maximum frequency of 5kHz for a 10kHz PWM carrier, as shown in his graph.

    So you are correct. If Fs = 1 is scaled to the PWM carrier frequency, the phase lag is twice per the diagram shown by Dave. 

    Regards,
    Martin Staebler

     



  • +1 in reply to Martin Staebler
    Intellectual 660 points

    Good morning Martin, thanks!

    Regards