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DRV8412 - using 1 power input for both GVDD PVDD

turg
Prodigy 50 points

Hi,

 

In a new design I would like to use one 24V power input for both PVDD (24V) and GVDD (12V), and to have as minor affect to other devices that connected to the 24V supply.

Therefore, a proper capacitor network must be designed in order to reduce the ripple and transients caused by the 24V PWM output.

What is the allowed ripple for GVDD?

Can you recommend on:

1) Design guidelines Documentation.

2) What can be used as simulation model. 

 

Thanks,

Tomer

  • 0
    TI__Guru 55605 points

    Tomer,

     

    The GVDD voltage needs to be in the range of 10.8V - 13.2V as specified in the datasheet.  So, 10% is the allowed ripple.

     

    1)  You can reference the datasheet, but I also attached a schematic from our DRV8412-C2-Kit.  The board takes a 24V supply and uses a buck to generate the 12V for GVDD and other circuitry on the evaluation module.

    2)  Currently, we do not have a simulation model for this device.  

     

    2543.DRV8412EVM_RevG-Schematic.pdf