DRV8706-Q1: LS FET turn off at <6mA gate current

Hi Piotr,

I guess "I strong" may be the cause of that phenomenon. I would try to change VGS_LVL and VGS_TDRV and see if it helps.

At first picture with normal waveforms rising time at OUT_B is around 400ns what is already quite a long time. I think extending it even further will only increase

switching losses. I would probably try to stay around 100ns and keep voltage overshoots at a bit lower level than on second picture.

Regards,

Grzegorz

Piotr,

Is there any update here with the suggestions above?

Regards,

Ryan

Hello,

Changing VGS_LVL setting does not bring any improvement.

VGS_TDRV was set to 4us. I tested all the other three values and:

- with 8us, the issue still occurs but for a lower gate current setting: <4mA (compared with <8mA with the 4us setting). So there’s and improvement;

- with 2us the issue remains unchanged;

- with 96us the issue distort the gate voltage slopes even more (see scope shot below).

So unfortunately your proposals do not solve the issue, issue, but only improve the chip behavior.

Given this:

1. Can you explain the mechanism by which you think the I_strong current might be the root cause?
2. Can you tell us why there is a very different value for VGS_TDRV (96us). I mean, I would expect that if there are options for 2, 4 and 8 us, the fourth one to be either 1us or 16us, but not 96us.
3. Can you propose some more investigations, settings etc?

Note: I don’t know if it’s important, but I mention that the MOS-FETs I used during tests have 1nF between Gate and Drain.

Hi Piotr,

1."Can you explain the mechanism by which you think the I_strong current might be the root cause?" - looking at the second picture from top the problem happens around 4us after LS gate started to turn off (4 us is longer than half of TDRV settings) + Figure 7-8. TDRIVE State Machine from DRV8706 datasheet.

" with 8us, the issue still occurs but for a lower gate current setting: <4mA (compared with <8mA with the 4us setting)" - that just confirms my suspicions.

2. "Can you tell us why there is a very different value for VGS_TDRV (96us). I mean, I would expect that if there are options for 2, 4 and 8 us, the fourth one to be either 1us or 16us, but not 96us." - Probably it is an error, I think Ryan should be able to confirm it.

3. "Can you propose some more investigations, settings etc?" - Not myself but I am quite sure it is I_strong that causes steep voltage slopes.

Can you tell why do you need switching times (time for OUT voltage to go from 10% to 90% or back) longer than 400ns?

Regards,

Grzegorz

Piotr F. said:

Please see below for more details.

Behaviour when Igate is higher than 8mA

I haven't read the chip registers to understand the effect of VGS_LVL and TDRV, but a quick look at the scope waveform leads to my question: Why the deadtime from G2H going low to G2L going high is about 800ns, but deadtime from G2L going low to G2H going high is only 400ns? Why not having them the same deadtime value for whatever it is?

Brian

Hey Piotr, 

Apologies for the delay, looks like we lost this post for a bit.  Several team members are out this week, but I'll do my best to support it.

This E2E post describes TDRIVE this way:  The TDRIVE gate drive timer makes sure that under abnormal circumstances, such as a short on the MOSFET gate or the inadvertent turning on of a MOSFET VGS clamp, the high peak current through the Smart Gate Driver and MOSFET gate is limited to a fixed duration". In essence, tDRIVE is fixed time that limits any abmornal circumstances like a short from potentially damaging the driver or motor.

Grzegorz Pelikan said:

2. "Can you tell us why there is a very different value for VGS_TDRV (96us). I mean, I would expect that if there are options for 2, 4 and 8 us, the fourth one to be either 1us or 16us, but not 96us." - Probably it is an error, I think Ryan should be able to confirm it.

I am not sure why 96us, agreed that it is very different than 1-4us.  Given the above explanation I would guess it is in case the customer really doesn't want these abnormal circumstances to happen.  Alternately, it could be a competitor part spec that we wanted to be compatible with.  I do not think it is an error. The large value could also be to give more selections of CSA_BLK since that is a percentage of the tDRV.  

Piotr F. said:

Can you propose some more investigations, settings etc?

Can you try adjusting ISTRONG by changing IDRVP? Could also try adjusting VGS_TDEAD, though unlikely to have an effect here.

Regards,

Jacob