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DRV8889-Q1: UVLO reset

Part Number: DRV8889-Q1

Hello,

I'm concerned about whether noise to the VM pin will cause IC reset.

The Data sheet said,
"When the voltage on the VM pin falls below the VM UVLO reset voltage (VRST, 3.9 V maximum), SPI
communication is unavailable, the digital core is shutdown, the FAULT and UVLO bits are low and the nFAULT pin is high."

How long does it take to reset if the VM voltage is kept below VRST ?
I couldn't find the description of the data sheet.
Please tell me. Regards,

  • Hey Fumika-san, 

    I also could not find this exact information in the datasheet.  There is some range of what value will result in UVLO from 4.15V minimum to 4.35V maximum (4.25V typical), so I'm sure that range also is a factor to when it will trip.  

    Let me ask our design team for this information.  It typically takes them 3-5 days to respond FYI.  

    In the meantime, I can assure you that noise on the VM pin causing IC reset is not a common problem for this device, and as long as you follow the recommended layout, bulk capacitors, and VM ranges I doubt you will encounter UVLO.  

    Regards,

    Jacob

  • Hi Jacob,

    Thank you for your response.

    We understand that IC reset due to noise on the VM pin is not a common problem for this device and UVLO does not occur.

    We look forward to your response to our inquiry.
    Best regards.

    Fumika

  • Hey Fumika-san, 

    I am still waiting on our design team to get back to me on this request, I pinged them asking for an update just now.  Should only be another couple of days.  Thank you for your patience.

    Regards,

    Jacob

  • Hey Fumika-san,

    Our design team said:

    Fast dip on VM below VRST can cause Digital reset in 20us with +/- 30% variation. 

    Regards,

    Jacob