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DRV8323R: Schematic Review

Part Number: DRV8323R
Other Parts Discussed in Thread: CSD88599Q5DC, CSD88584Q5DC, CSD87334Q3D, DRV8323,

Hi TI Team,

I'd like to see if you could give this design a quick glance to see if I missed out on any important connections within the schematic, I was following the design guidelines of your spec sheets and application notes.

Specs of the design:

  • 20A Max at 26.7 V MAX
  • Single shunt resistor sensing, using only one current sense amplifier (SOA) to sense motor current
  • The DC-DC Switch regulator of the DRV device will supply the system with 3.3V at150mA MAX
  • 1xPWM Configuration
  • DRV is controlled/communicates with by an external MCU. 

Please let me know if you have any feedback or any more questions. I'll supply and respond as fast as I can.

  • Hi Patryk,

    CSD87334Q3D is a power block designed rather for DC/DC buck converters, I think a better option would be half-bridge like CSD88584Q5DC or CSD88599Q5DC.

    Regards,
    Grzegorz

  • Hello Grzegorz,

    Thanks for your feedback, I have selected the CSD87334Q3D due to its size and also TI had described it for motor control, we are working on a small area board unfortunately. Would you say there would be major issue when going with the CSD87334Q3D rather than the half-bridges you mentioned? 

    Regards,

    Patryk.

  • Hi Patryk,

    CSD87334Q3D is half-bridge optimized to work in DC/DC converters, its best efficiency is in the area of 300kHz - 1MHz while motor drives usually work somewhere 10 - 100kHz. In DC/DC buck converters HS mosfet is optimized for switching losses while LS Mosfet is optimized for conductive ones, though in case of CSD87334Q3D both mosfets seem to be the same. I guess it would be easier to get lower power losses with half-bridges like CSD88584Q5DC than with CSD87334Q3D unless high switching frequency was needed.

    Looking at DRV8323 and CSD87334Q3D datasheets we can notice that CSD87334Q3D is optimized for 5V gate driver with absolute max. voltage of 10V. DRV8323 HS gate driver voltage (Vgsh) can go up to 12.5V, what will happen if gate driver delivers 12.5V to CSD87334Q3D?

    - will CSD87334Q3D be destroyed?

    - will CSD87334Q3D internal diode (I guess some protection diode) start to conduct limiting gate voltage to 10V? Will it lead to GDV fault?

    - if protection diode starts to conduct will its recovery charge change mosfet switching behaviour?

    I do not say that is not possible to use CSD87334Q3D in your application but it may bring a few extra problems that will have to be solved.

    Regards,

    Grzegorz

  • Thank you very much for explaining this to me. I always found it challenging to understand the power stage of a BLDC driver and all the help I can get to understand it is very appreciated.

    Kind regards,

    Patryk Szczesny.

  • Hey Patryk,

     

    Please find the attached PDFs with the schematic review.

     DRV Schem1- TI Reviewed.pdfDRV Schem2 - TI Reviewed.pdfDRV Schem3 - TI Reviewed.pdf

    Best Regards,

    Akshay

  • Thank you for the review Akshay, going over your comments. The pull ups for the SPI lines are going to be located on the MCU side of the project, unless it would be more effective closer to the DRV device?

    And on the schematic 2, yes that's where the low sides are connected to the SPA and SNA. As for the half-bridges I am now asking the design department to allow for a PCB size change so that we can fit the recommended bridges.

    Regards,

    Patryk.

  • Hi Patryk,

    Decoupling caps C3,C4 and C5 in your design are grounded to GND (bottom of sense resistor), on BOOSTXL-DRV8323RH evm board those caps a grounded to the top side of sense resistors. The first solution works OK with lower currents while the second one is better for higher currents. For a 20A driver both of them should work. With high currents and high di/dt there are high voltage spikes and ringing on sense resistor due to its parasitic inductance. The second solution places sense resistors outside high di/dt loop. For a 20A driver 100nF caps might be more suitable.

    If its your first design of such driver I would first check if all major required functions work well on evm board and then use evm board as a start point to design my own PCB (layout is very important).

    Regards,

    Grzegorz

  • Hey Patryk,

     

    For SPI our recommendation is to route is differentially away from sensitive analog signals (CSA outputs).

     Open-drain outputs such as SDO and nFault shouldn’t be too long.

    Pull-up resistor on SDO line should be placed close to the pin of the DRV.

     

    Hope this helps.

     

    Best Regards,

    Akshay