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Original question:

DRV8718-Q1: VDS overcurrent fault report

DRV8718-Q1: gate and source waveform

Elec Cheng
Expert 7055 points
Part Number: DRV8718-Q1

Hi Expert,

I test DRV8718-Q1 EVM and test gate voltage and source voltage. This part schematic is as below. I change different Idrv and get different wave from. All test is under no load.

1. I set IDVR= 62mA. Yellow line is gate voltage(GH1)  and blue line is source voltage of high side (OUT1). Actually I cannot see the Miller Plateau. Is it normal that we don't often capture it? And also, the rising waveform and falling waveform is not the same. For the falling waveform, there is a platform but OUT voltage stays. Is it Miller Plateau?

2. Then I change IDRV to 0.5 mA. The test waveform is as below. The rising part and falling part are not the same trend still. And the the platform is much longer. Could you please help explain that? Thanks.

BR,

Elec Cheng

  • 0
    TI__Mastermind 44835 points

    Hi Elec,

    Thank you for  your questions. 

    Your waveform looks normal. With 64mA, driving current is very strong. You see similar waveform as datasheet when you reduce current to 0.5mA.

    regards

    Shinya Morita

  • 0 in reply to Shinya Morita
    TI__Expert 7055 points

    Hi Shinya,

    Thanks for your reply! For the test waveform above, I have several confusion:

    1. The rising edge and falling edge is not identical as you show, no matter under strong Idrv or weak Idrv. What's the possible reason?

    2. The flat part of GATE falling edge, is it Miller Plateau? If yes, then why out voltage is still flat instead of going down? If no, then what is it and why it happens like this? 

    I am promoting DRV8718-Q1 to the customer will demonstrate to them with EVM. Please kindly help! Thanks.

    BR,

    Elec Cheng 

  • 0 in reply to Elec Cheng
    TI__Mastermind 44835 points

    Hi Elec,

    1.2.  It can not be symmetrical due to FET's characteristic or motor current behavior. If you disconnect motor and no load, you may have different waveform.

    Thanks,

    regards

    Shinya Morita

  • 0 in reply to Shinya Morita
    TI__Expert 7055 points

    Hi Shinya,

    Elec Cheng said:
    All test is under no load.

    The waveform above are all under no load. Could you please help explain the question I list above? Thanks.

    BR,

    Elec Cheng

  • 0 in reply to Elec Cheng
    Genius 3700 points

    Hi Elec,

    It would make an analysis easier If you could use differential probe for GH1 (between GH1 and SH1) or use math function (GH1 - SH1). Could you also add GL1 signal? I think there is visible Miller plateau on rising edge because GH1 signal is causing change in Vds voltage of HS Mosfet. I think there is no Miller plateau on falling edge because GH1 signal is not causing change in Vds voltage of HS Mosfet, I guess it is caused after dead time by LS Mosfet.

    If you could make a picture of (GH1-SH1), SH1 and GL1 signals it could help to understand what is going on in that half-bridge but I think all pictures above look OK.

    Regards,

    Grzegorz

  • 0 in reply to Grzegorz Pelikan
    TI__Mastermind 23421 points

    Hey Elec,

    I think Morita-san is saying that the lack of symmetry is due to internal characteristics of the FET.  It isn't supposed to be perfectly symmetrical or identical on the rising and falling waveform.  Waveforms above don't look problematic. 

    Regards,

    Jacob