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DRV8434S: Operation of FAULT signal

Taito Takemura
Expert 3220 points
Part Number: DRV8434S

Hi experts,

Could you please answer questions below about FAULT signal?

(1) Since the FAULT signal can be cleared by CLR_FLT (SPI) or nSLEEP (I/O), there is no condition that only CLR_FLT (SPI) or only nSLEEP (I/O) can clear it. Is my understanding correct?

(2) According to the datasheet, FAULT can be cleared in two ways, CLR_FLT (SPI) or nSLEEP (I/O). Could you tell me why you set up two ways?

(3) Since it can be cleared by CLR_FLT (SPI) or nSLEEP (I/O), is there any problem in using either CLR_FLT (SPI) or nSLEEP (I/O)?

(4) Is there a level (priority) set within the device for the FAULT condition?

(5-1) When power is applied to the board, is it correct that the FAULT signal is Hi during the period when the VM of the device is at a low voltage?

(5-2) ( When power is applied to the board) If the UVLO bit is not cleared, it remains latched to Hi. So clear processing is required when the board receives power. Is my understanding correct?

Thank you for your help.

Best Regards,

Taito Takemura

  • 0
    TI__Mastermind 23421 points

    Hey Takemura-san,

    Taito Takemura said:
    (1) Since the FAULT signal can be cleared by CLR_FLT (SPI) or nSLEEP (I/O), there is no condition that only CLR_FLT (SPI) or only nSLEEP (I/O) can clear it. Is my understanding correct?

    Correct, you should not need both GPIO and SPI to clear anything.

    Taito Takemura said:
    (2) According to the datasheet, FAULT can be cleared in two ways, CLR_FLT (SPI) or nSLEEP (I/O). Could you tell me why you set up two ways?

    Flexibility for the customer.  Some customers might want a GPIO way to reset fault, others use SPI communication for everything.  Just good options.  

    Taito Takemura said:
    (3) Since it can be cleared by CLR_FLT (SPI) or nSLEEP (I/O), is there any problem in using either CLR_FLT (SPI) or nSLEEP (I/O)?

    Nope, use whatever you want!

    Taito Takemura said:
    (4) Is there a level (priority) set within the device for the FAULT condition?

    No priority, whatever happens first.  Table 7-10. Fault Condition Summary you posted is a great reference for what happens during each condition.  

    Taito Takemura said:
    (5-1) When power is applied to the board, is it correct that the FAULT signal is Hi during the period when the VM of the device is at a low voltage?

    The device is powered by VM, so when VM < 4.5V the device will be off and all pins will likely be Hi-Z unless they have an external pull up/down.  Given nFAULT should have an external pull-up resistor, yes, nFAULT would read HIGH to a MCU during this time as long as the VCC nFAULT pullup resistor connected to is high.  I think I am not understanding your question correctly? 

    Taito Takemura said:
    (5-2) ( When power is applied to the board) If the UVLO bit is not cleared, it remains latched to Hi. So clear processing is required when the board receives power. Is my understanding correct?

    UVLO only is enabled after the device "boots up", so UVLO bit does not need to be cleared when device is powered up.  

    Regards,

    Jacob

  • 0 in reply to Jacob Thompson
    TI__Expert 3220 points

    Hi Jacob,

    Thank you for your answer.

    I have an additional question. Could you please answer it?

    (6) Is it necessary to resend the parameters before the FAULT occurred if a FAULT occurs and it is cleared by the CLR_FLT bit or nSLEEP reset pulse and normal operation can resume? This is a question to check whether the above series of operations only clears the FAULT signal and does not clear the parameters

    Best Regards,

    Taito Takemura

  • +1 in reply to Taito Takemura
    TI__Mastermind 23421 points

    Hey Takemura-san,

    Do not need to resend parameters after CLR_FLT or nSLEEP pulse.  You would only need to resent parameters if the supply voltage VM dipped below VRST UVLO reset as shown in Figure 7-20. Supply Voltage Ramp Profile

    Cheers,

    Jacob