Hello,
For DRV8714-Q1, if cut off the DVDD and still keep the PVDD, what will be the status of GHX/SHX/GLX? Do customer need to pull up the BRAKE pin if customer need TO KEEP GHX/GLX to low? Thanks!
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Hello,
For DRV8714-Q1, if cut off the DVDD and still keep the PVDD, what will be the status of GHX/SHX/GLX? Do customer need to pull up the BRAKE pin if customer need TO KEEP GHX/GLX to low? Thanks!
Hey Tom,
Just for clarification: By "cut off the DVDD", do you mean it will be set LOW to 0V, or will it be left floating like if disconnected by a load switch?
And which mode will this be in - Half-bridge control, H-bridge control, split HS/LS control? Any other circumstance details you could give?
Let me put in a design ticket for this question. It will take them 3-5 business days to get back to us.
Cheers,
Jacob
Hi Tom,
For DRV8714-Q1, if cut off the DVDD and still keep the PVDD, what will be the status of GHX/SHX/GLX? Do customer need to pull up the BRAKE pin if customer need TO KEEP GHX/GLX to low? Thanks!
If the customer want to keep GHx and GLx low, then they should have BRAKE=low and not high. If BRAKE=hi then the GLx will be high to turn on all lower FETs to have the motor in brake mode.
From datasheet, when DVDD is low, this condition is the same as having nSLEEP=low. The state of GLx depends on the logic at BRAKE pin, see 2 below.
1. "If at any time the input logic supply voltage on the DVDD pin falls below the VDVDD_POR threshold for longer than the tDVDD_POR_DG time or the nSLEEP pin is asserted low, the device enter its inactive state disabling the gate drivers, charge pump, and protection monitors. "
2 . "The DRV871x-Q1 provide the ability to enable the low-side gate drivers while the device is in its low-power sleep mode (nSLEEP = logic low). This allows the external low-side power MOSFETs to be enabled while maintaining a low quiescent current draw from the power supply. Enabling the external low-side MOSFETs allows the device to actively brake a motor connected to the external half-bridges by shorting the back emf across the motor terminals. This can help prevent reverse driving of the motor by an external force from overcharging the system power supply by dissipating the energy in the low-side MOSFETs. This function is only available while the device is in its low-power sleep mode. The function is enabled by taking the BRAKE pin to logic high."
Brian
Hi Jacob,
Yes, in this situation customer will power off the DVDD but keep the PVDD. They don't do any action on Brake pin. They are using it in door module, it is H-bridge application.
Hey Tom,
Thanks for the info. Our design team actually already got back to me:
If DVDD level(whether forced or if it droops due to current on disconnecting) is below POR level the device behaviour would be same as sleep mode behaviour.
Let me know if you need any other clarification.
Cheers,
Jacob