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DRV8889-Q1: UVLO reset

TEZUKA FUMIKA
Prodigy 150 points
Part Number: DRV8889-Q1

Hello,

Let me ask you two questions about UVLO specifications.

１．UVLOLockout
The data sheet said that when the VM pin falls below the UVLO falling threshold voltage, all the outputs are　disabled (High-Z).   (drv8889-q1 page 34  VM Undervoltage Lockout (UVLO))
At this time, if Open-Load Detection (OL) is enabled (EN_OL is High), will the OL bit of FAULT Status be TRUE?

2.UVLO reset
We recognize that the register setting is cleared when the VM pin falls below the VM UVLO reset voltage.
I want to detect the UVLO reset and set registers.
Please let me know if there is any recommended usage.

Regards,

  • +1
    TI__Guru 55605 points

    Fumika-san,

    1)  It is possible to get OL bit set during the condition you describe.  This should be ignored.  

    2)  One method is to check status on nFAULT.  nFaULT will drop low at VM UVLO and then go back high at UVLO reset.  If they monitor nFAULT and see this behavior, then UVLO reset can be detected.  Another method would be to check for a reset of any of the bits.  If bits are flipped to a different state than expected, a reset has occurred.

    Regards,

    Ryan