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DRV8301: Disabling the driver

Gerald
Genius 9570 points
Part Number: DRV8301

Hi Experts,

The customer is using the DRV8301DCA in an ESC and needs to be able to ensure that the ESC does not engage the motors on startup, and he is required to have a safety override to ensure it cannot be accidentally controlled when not necessary. 

He was thinking that he could use the EN_GATE pin as this control. What happens to the chip if it is held low indefinitely (minutes to hours)? Does this cause any form of damage? Once he drives EN_GATE high again, will the 8301 return to an operational state or does it need a POR at that point?

Let me restate them:

1.) "What happens to the chip if it is held low indefinitely (minutes to hours)?"
2.) "Does this cause any form of damage?"
3.) "Once I drive EN_GATE high again, will the 8301 return to the operational state or does it need a POR at that point?"
4.) "Also, does holding EN_GATE low shut off the buck converter or affect it in any way?"

We hope to receive your confirmation/advise. Thank you.

Best regards,

Gerald

  • 0
    TI__Mastermind 23476 points

    Hey Gerald,

    I will aim to provide feedback next week.

    Best,

    Akshay

  • 0 in reply to Akshay Rajeev Menon
    TI__Mastermind 23476 points

    Hey Gerald,

    I don't expect to see an issue in holding EN_GATE low for an extended duration of time. 

    EN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks into a low-power consumption mode to save energy. SPI communication is not supported during this state and the SPI registers will revert to their default settings after a full EN_GATE reset. The device will put the MOSFET output stage to high-impedance mode as long as PVDD is still present. When the EN_GATE pin goes low to high, it will go through a power-up sequence, and enable gate driver, current amplifiers, charge pump, internal regulator, and so forth and reset all latched faults related to gate driver block. The EN_GATE will also reset status registers in the SPI table. All latched faults can be reset when EN_GATE is toggled after an error event unless the fault is still present. 

    I suggest reading section 7.4.1 for more info.

    The buck is controlled through a separate EN_BUCK pin. So EN_gate will not affect buck as long as buck is receiving its own power.

    Hope this offers some clarification.

    Best,

    Akshay

  • 0
    Genius 5040 points
    Gerald said:
    What happens to the chip if it is held low indefinitely (minutes to hours)? Does this cause any form of damage? Once he drives EN_GATE high again, will the 8301 return to an operational state or does it need a POR at that point?

    Hi Gerald,

    Since the EN_GATE has 100K internal pull down, by design this means holding this pin low indefinitely will not cause harm to the chip.

    After EN_GATE going high for 10ms, the chip should be ready based on datasheet:

    Brian