DRV8353: IC permanently damaged during supply interrupt test

Hey Dragos,

Thank you for your question.

I will aim to provide feedback next week.

Best,

Akshay

Hey Dragos,

Could you tell me what pins are measured in the waveforms shown?

Best,

Akshay

Hello Akshay,

These variables are a mix of DRV physical signals and SW variables related to motor control disabling phase.

VDRAIN = Blue Color Waveform

Motor Phase U Current = Yellow Waveform

Motor Phase V Current = Green Waveform

PWM Duty Cycle (phase U) = RED Waveform

As mentioned initially Test Condition: VM = 15V during the test. VDRAIN drops from 25V to 0V. Motor Phase Currents with 0RPM / PH_U=+5A / PH_V=-2.5A / PH_W=-2.5A.

When VDRAIN reaches 17V (BLUE trace), COAST bit is set = 1 to force the FETs in Hi-Z, since this is the threshold level of Lower Operating Motor Range.

1.Could this COST=1 request create permanent damages on internal Charge Pump having VDRAIN dropping to 0V? (while VM = 15 V remains)

2.Just after COST=1 request, the input PWMs are set to 50%. Can you confirm that COST bit overwrites the PWM requests and this can't lead to an Charge Pump damage?

3. In case ENABLE pin is toggled low - for reconfiguration after VDRAIN gets back to normal levels, having PWM inputs set to 50%. Could this active PWM present during twake = 1ms, lead to a permanent damage of the internal Charge Pumps?

Hey Dragos,

Thank you for the clarification. I will aim to provide feedback before the end of the week.

Best,

Akshay

Hey Dragos,

Based on the description the VM and VDrain have separate sources, so I am curious to know how you are decreasing Vdrain, Are you disconnecting the battery? And is VM always 15V throughout the experiment?

By setting the coast bit all the FETS are turned off so the current would recirculate through the body diodes and back into the supply. Did the gate to source short occur when you turned on coast at 17V Vdrain?

Could you provide the gate to source and drain to source voltages? Is nfault being triggered? If so please provide waveform along with the VGS and VDS and VCP

The coast bit should override the input PWM signals. 

We dont expect the PWM present during twake to lead to charge pump damage..

Best,

Akshay

.

Hello Akshay,

VM is constant at 15V kept stable for about 200ms. The microcontroller and the DRV are operating correctly during this time.

VDRAIN drops to 0V in 1ms - the battery is disconnected - for about 20ms.

NFAULT is activated, when VDRAIN reaches about 6.4V. In the same moment, some flags are set in the Status Registers 1 & 2 (please check the updated picture from original post).

When VDRAIN gets back to nominal 28V, DRV can't be restarted even if ENABLE pin is toggled to clear the registers. It has a permanent damage, caused by short of GLC(pin18)-to-SPC(pin19).

The damaged occurred either, during VDRAIN dropping phase, either during reinitialization (after VDRAIN gets back to nominal) having 50% PWM on the inputs.

Of course during initialization COAST bit is also cleared (registers set to default), and 50% PWM is applied to the MOS-FETs during Charge Pump settling time twake =1ms.

We don't know what cause the damage, since in normal operation, VDRAIN is always >=17V and <=32V and we didn't had failures, controlling the FETs.

I could also send you some Osciplots, but since this is confidential info, please provide your company email.

Thanks! Dragos

Hey Dragos,

Thank you for the clarification. I will bring this up with the team and plan to move this conversation to internal only.

Best,

Akshay

Hi Dragos,

Dragos Moscalu said:

Gate-Source short is present on DRV output pins GLC(pin19)-to-SPC(pin19) ~4.7 ohms.

First, GLC and SPC can not be the same pin19, and then without knowing the driver package option -- 8353xxx -- nobody can read your mind to confirm the pins.

Dragos Moscalu said:

Test Condition: VM = 15V during the test. VDRAIN drops from 20V to 0V

Reviewing the waveform, it seems VDRAIN drops from 25v and not 20v; so why say 20v instead of what it is? On the same waveform, both V and U phases are labeled as V; ???

The PWM-duty cycle  waveform with logic high is only 0.55v which seems abnormal -- is this the signal at the PWM input pin or other location?

Dragos Moscalu said:

When VDRAIN gets back to nominal 28V, DRV can't be restarted even if ENABLE pin is toggled to clear the registers. It has a permanent damage, caused by short of GLC(pin19)-to-SPC(pin19).

For some reasons your last post repeated the same typo of GLC and SPC are the same pin19. This makes me think pin19 of some package option has the magic of providing multiple functionality -- namely GLC and SPC. Can you comment on this?

Dragos Moscalu said:

The damaged occurred either, during VDRAIN dropping phase, either during reinitialization (after VDRAIN gets back to nominal) having 50% PWM on the inputs.

Well, this can be easily identified: measure the resistance from GLC to SPC after VDRAIN turned off, then do it again after reinitialize the driver with VDRAIN powered up. Not too hard isn't it?

Brian

To Summaries the Problem and answer the questions from Dang Brian: 

Device affected DRV8353SMRTAT in 40-pins VWQFN package.

DRV Damage Effect: Gate-Source short is present on DRV output pins GLC(pin18)-to-SPC(pin19) ~4.7 Ω. MOS-FETs are not affected by the DRV damage. The short is present with board unpowered. It doesn't matter if VDRAIN is turned off (disconnected), or ENABLE line is low, the 4.7 Ω is present all the time.

Test Condition that leaded to this Damage:
In normal operation device works fine, even with relatively large Motor Phase Currents +/-20A.
The problem occurred during system Power Supply Interruption – 24V drops to 0A (tfall=1ms), and stays at 0V for 120ms, then returns to 24V (trise=1ms)
The IDRIVEx registers setting are set as following:
IDRIVEP_LS = 0010b = 100mA & IDRIVEN_LS = 0010b = 200mA
IDRIVEP_HS = 0011b = 150mA & IDRIVEN_HS = 0010b = 200mA
Driven MOS-FETs: IAUT150N10S5N035ATMA1

VM = 15V remains constant during the test. VDRAIN drops from 24V to 0V. Motor Phase Currents with 0RPM / PH_U=+5A / PH_V=-2.5A / PH_W=-2.5A.
The official test condition is a voltage drop from 17V to 0V, but actually the initial voltage doesn't matter that much.

Software Control:
When VDRAIN reaches 17V, COAST bit is set = 1 to force the FETs in Hi-Z, since this is the lower threshold level of System Operating Range.
Just after the COAST bit set to 1, PWM DutyCycle is set to 50%. As can be seen in the next plot, DRV goes in UV caused by VDRAIN 6.4V which is OK (confirmed by Status Registers readings)

For the attached plot, I've added the measurement unit for each signal. PWM is in % Duty Cycle, so we see that it tries to compensate the VDRAIN voltage drop until COST bit is set to 1, by increasing with 2%. Then is permanently set to 50%.

Some Questions have been already answered by Akshay Rajeev:

1.Could this COST=1 request create permanent damages on internal Charge Pump having VDRAIN dropping to 0V? (while VM = 15 V remains)

No, since the Motor Currents will continue to flow on the Body Diodes, of the MOSFETs.

2.Just after COST=1 request, the input PWMs are set to 50%. Can you confirm that COST bit overwrites the PWM requests and this can't lead to an Charge Pump damage?

Yes, COST overwrites the PWM commands.

3. In case ENABLE pin is toggled low - for reconfiguration after VDRAIN gets back to normal levels, having PWM inputs set to 50%. Could this active PWM present during twake = 1ms, lead to a permanent damage of the internal Charge Pumps?

Normally not, as suggested by Akshay Rajeev. But the datasheet suggest on Page 42: "The tWAKE time must elapse before the device is ready for inputs."

4. We are not sure if the damaged occurred during VDRAIN dropout or during DRV re-initialization phase, when VDRAIN returns to normal levels - Not confirmed yet by TI.

We have another assumption, that during reinitialization, when ENABLE line is toggled, the FETs are switching with 50% Duty Cycle, by using the default register settings, for about 2ms until the SW reconfigures the device registers. 

5. Can you confirm if this 50% PWM during initialization (including twake=1ms), could create a permanent damage on the device, due to operation with DEFAULT Register Settings. We know that with DEFAULT Registers, we might violate the -5V on SLx DRV pins, when operating on large motor currents +/-20A, but we are not sure if the same effects are happening with 50% Duty Cycle.

Attached I've also added some measurement results, in an excel file, just for the moment when COAST bit is set to 1. To be mentioned that P28V_FLT = VDRAIN. During this tests, to be able to capture more waveforms, VDRAIN was not forced below 6.5V since we couldn't afford to damage another board. For this reasons, some other Loads have been disabled to preserve the capacitor voltage storage (3 x 330uF Capacitors), so that VDRAIN remains still high enough, to catch the events during COST bit activation, without activating the UV caused by VDRAIN dropout.

GDU POWER INT - OsciPlots TI.xlsx

Hey Dragos,

Thank you for the waveforms.

1) Could you coast the motor without powering down Vdrain to see if the damage is occuring?

2) You mentioned this is the second time this has happened as in you have only tested two ICs or that only 2 out of the x number of ICs tested saw this damage?

3) In order to determine when the damage occurred, check for the short after lowering Vdrain and before reinitialization. And if no damage present then reinitialize Vdrain and see if damage present.

4) I also want to check how fast the coast bit is being set. Could you provide waveform of Vdrain, GLA, GLB and GLC as you power down Vdrain and set coast bit at 17V?

5) Why are you suspecting a charge pump damage? Did you observe any concerns? Since low side is supplied through VGLS and not charge pump.

6) What all faults were reported?

Best,

Akshay

Hi Dragos,

Dragos Moscalu said:

NFAULT is activated, when VDRAIN reaches about 6.4V. In the same moment, some flags are set in the Status Registers 1 & 2 (please check the updated picture from original post).

On the waform, nFAULT should be an active low signal -- low means fault and high means normal. Then why nFault is low when Vdrain is above 20V (the waveform with label says "SW state" meaning the graph waveform represents the software status bit value, not the nFault output signal? (But then the graph seems to have slow rise time, which cannot be a status bit that has a slow rise time. I'm so confused).  

I think the driver chip was damaged due to all output were high-Z at relatively high motor speed with high BEMF that feedback to the driver. Why to coast instead of brake which is safer with 3 lower FETs turned on?

Brian

Hello Akshay,

1) This is exactly what I've did to record the plots from - GDU POWER INT - OsciPlots TI.xlsx. VDRAIN was kept above 6.4V by disconnecting other loads. So NFAULT and UV flags are not triggered. No DRV damage occurred during my tests, by activating the COAST bit - even operating at +/-10A on that Phase (compared to +/-5A as initially tested). I can conclude, no DRV damage occurred if VDRAIN was above Vvdrv_uv = 6.4V. 

2) We've operated several boards ~10 with currents up to 20A. The damage occurred on two boards, and only during Power Interruption Tests. To be mentioned the damage didn't occurred immediately, on the first run. Rather after interruption time was increased, and VDRAIN started to get lower, until UV flag was triggered at 6.4V. We've applied ~10 interruption with times of 3ms, up to 100ms, and then DRV was damaged. If we try on other boards, most probably the event will occur again.

3) Damage is permanent with DRV even unpowered. If VDRAIN is set to 0V and VM=15V, the 4 ohms short is seen between GLC(pin18)-to-SPC(pin19). Of course if powered, the Status Register flags are also visible. Disabling the device ENABLE = Low, doesn't change the situation - permanent 4 ohm short on GLC(pin18)-to-SPC(pin19).

4) VDRAIN is P28V_FLT trace is some pictures from attached Excel file. As can be observed in the first 7 pictures VDRAIN is ~15V when COAST is set.

5) I've suspected the CP since this output is made from VDRAIN. I wasn't aware that VGLS is not using the CP at all.

6) NFAULT pulled low. Fault Status Register 1 - Bit 7 UVLO and Bit 10 FAULT. Fault Status Register 2 - Bit 6 GDUV

Hello Brian,

In the waveform plot FAULT is a Software state, meaning that when HW NFAULT was activated = Low in our Software it goes to High.

Yes, you are right the graph was quire low resolution ~1ms, this is a capture of parameters from SW, to better understand the test sequence. Please have a look into the attached Excel file for HW plots, captured with the Oscilloscope.

The test was performed without the Motor. Only Static Loads, L and R. So there is no rotation, Speed is = 0 RPM, angle is fixed to have +5A on phase U / -2.5A on the other two phases.

Additional info about the failure, with DRV8353SMRTAT unpowered (VM=VDRAIN=open), I've measured the following resistances - with a regular multimeter:

VGLS(pin40) to Ground Plane = 2.93 ohms

GLC(pin18) to SPC(pin19) = 3.64 ohm

VGLS(pin40) to GLC(pin18) = 4.81 ohm

VGLS(pin40) to SPC(pin19) = 2.6 ohm

Hey Dragos,

Thanks for the additional information.  I will get back to you early next week.

Best,

Akshay

Hello Akshay,

Do you have some updates related to this topic?

Hey Dragos,

Apologies for the delay. We are following up on items after the holidays.

Please expect a feedback before the end of the week from our team. Would you be able to provide your schematic for review?

Best,

Akshay

Hello Akshay,

Before sharing the schematic, I would like to mention that was already reviewed by TI together with the layout a few years ago, so there is a low probability to find something new. Especially since in normal operation, everything works fine - it's just the Supply Interruption that causes these problems.

We did several investigations these days, and we thing the problem is related to the initialization phase when ENABLE line is released.

In the following plots you will notice that ENABLE is not stable. Can you confirm that this kind of oscillation could damage the DRV. It can be observed also that VGLS and VCP didn't reached the nominal level, but the input PWM demand is present, requiring to control the external FETs(in some cases).

Can you provide your observation, focusing on the unstable ENABLE line and the influence on the DRV chip internal supply initialization. We assume at some point the VGLS linear regulators could be affected, but we don't have a clear overview of the internal architecture. Also VCP charge pump will demand some inrush current from VM that could lead to some overheat ... these are just assumption since we don't know how the chip will handle the fast ENABLE toggling.

Thanks,

Dragos