Original question:
DRV8718-Q1: PWM frequency& duty cycle accuracy through HBx_CTRL SPI control register
Hi team,
My customer said for the INX PWM input signal, if they set duty cycle to 10% or 20%, the half-bridge gate drivers can't output and is always low. If they increase the duty cycle ≥30%, the gate drivers output is fine.
Could you please help to explain? Is it normal?
Thanks!
Hi,
Thank you for your question. If DRV's output turned off, some fault condition may happened by changing duty cycle.
Here is suggestion for debug.
-Read back following status registers. It will tell what type of fault happens. Then fix the issue based on fault conditions.
For example, if VDS over current fault happened, adjust proper VDS threshold by SPI register.
- Keep monitoring nFAULT pin and try to capture nFAULT low timing. Something may happens when nFAULT goes to low. e.g PVDD, voltage supply drop, higher motor current etc.
regards
Shinya Morita
