DRV8329: PWM control mode of DRV8329 && PWM generate issue

Hi Sal,

Thank you for posting to the Motor Drivers forum!

Unfortunately, I did not get to look at this today, but I will get back to you with a response shortly.

Best,

~Alicia

Hi Alicia,

Thanks and I look forward to your reply.

Here are some update and I have edit thread via read color.

Meanwhile, it happens a new cases, hope you can help me figure it out:

P2-Abnormal

Background: Connected power supply pin, set INHA & INLA on with PWM, then measure OUTA voltage. (Totally same configuration with P0)

When I just switch nSLEEP_SW repeatedly, then sometimes it will show fault signal, and sometimes it show normal. Also, it seems no regularity.

Note: I am sure that I have trigger a low logic signal longer than 1us, I have tested maybe 10~100ms(quickly), or 1~2s(slowly). And, when I trigger a slowly low logic reset signal, it (which is fault happens) will occur more frequently. 

I am not sure what makes this happen.

Thanks and Best Regards

Sal

Hi Sal,

Regarding your first question, the DRV8329 has 2 variants: the DRV8329A (which supports PWM Mode 6x) and the DRV8329B (which supports PWM Mode 3x). 

At the moment only the DRV8329A variant is available as specified by the following:

So at the moment, only the 6x PWM mode is available.

To clarify, for the waveforms that you have shared, does the pink line for the gate driver waveforms represent INHx or INLx? Which one does the blue line represent? Also, what do the pink/blue lines represent in the OUTA waveform? Is it the GHx/GLx/SHx?

Do you know what could be causing the fault to occur? If not, try monitoring the voltage for the following pins: PVDD, AVDD, GVDD, and the voltage across BSTx and SHx.

Best,

~Alicia

Hi Alicia,

Thanks for your reply, I understand DRV8329B is not available now.

Here is the instruction for the signal I graphed.

Gate driver:

Pink: INHx (INHA)    Blue: INLx (INLA)

OUTA:

Pink: OUTx (OUTA)    Blue: GND(not used)

nFAULT: ~0V. Fault happens. It is not clearly what causes fault.

Pink: nFAULT     Blue: GND(not used)

I have not clearly idea what caused fault, but it seems that fault occurs when DRV goes into Hi-Z at normal operation. Is it possible?

By the way, I am on vacation now, so if you need any more test data I may clarify it 1-2 weeks later. If you can give me some possible guess based on currently data will be helpful. Thanks~

Best Regards

Sal

Hi Sal,

When you get back from your vacation, can you monitor the following when as fault occurs:

• GVDD 
• Voltage across BSTx and SHx pins
• V_DS voltage drop across R_DS(on)
  • High-side: Voltage across PVDD and SHx pins
  • Low-side: Voltage across SHx and LSS pins
• Voltage drop across external current sense resistor between LSS and GND pins

Based on the voltage levels that you are able to observe as this fault occurs, it should help to narrow down what fault is occurring.

Best,

~Alicia

Hi Alicia,

Here is the update, I think it normal when operate in Hi-Z mode.

When I set the DRV8329AEVM board input as below:

 (Green is OUTA; pink is GHA; blue is GLA; all connected to GND)

So, considering there is no load for OUTA, so capacitor make the voltage maintain. Does this make sense?

• Voltage across BSTx and SHx pins

• V_DS voltage drop across R_DS(on)
  • High-side: Voltage across PVDD and SHx pins
  • Low-side: Voltage across SHx and LSS pins

 (Green is High-side: PVDD->SHx)

• Voltage drop across external current sense resistor between LSS and GND pins

Best Regards

Sal

Now if the phenomena in the previous replies is correct, there remains only the question that for operation timing for DRV, shown as below:

Sal Ye said:

Meanwhile, it happens a new cases, hope you can help me figure it out:

P2-Abnormal

Background: Connected power supply pin, set INHA & INLA on with PWM, then measure OUTA voltage. (Totally same configuration with P0)

When I just switch nSLEEP_SW repeatedly, then sometimes it will show fault signal, and sometimes it show normal. Also, it seems no regularity.

Note: I am sure that I have trigger a low logic signal longer than 1us, I have tested maybe 10~100ms(quickly), or 1~2s(slowly). And, when I trigger a slowly low logic reset signal, it (which is fault happens) will occur more frequently. 

I am not sure what makes this happen.

It can be summarized as follows:

1. When INHx&INLx is input ahead of DRV powered up, DRV always make itself fault after powered up.

Note: This makes me wrongly believed that Hi-Z mode would cause DRV error.

2. There need a nSLEEP_SW action to release error. However, it need a short low logic signal, which seems not mentioned in datasheet. A long low logic signal of nSLEEP always make the error insist (rarely times error disappear).

Can you give me some explanation for these two situation. Truly Thanks.

Best Regards

Sal

Hi Alicia,

Thanks for answering the question for the tRST. I get it.

What about the question below:

Sal Ye said:

1. When INHx&INLx is input ahead of DRV powered up, DRV always make itself fault after powered up.

How this happens? Do you have any comments on this?

This situation will cause that when apply to motor control, it is necessary to set DRV nSLEEP a low logic signal when system begin. 

Best Regards

Sal

Hi Sal,

Sal Ye said:

However, I don't find any hardware pin number to settle it PWM mode. Can you give me some suggestions?

If you don't know how to set what PWM mode, then why you referred to the 6x PWM Table for your questions?

Brian

Hi Brian,

In the first, when I use 6xPWM for test, there is no other error, so I assume 6xPWM is available.

Then, Alicia has nicely give me the feedback as below:

Alicia Rosenberger said:

Regarding your first question, the DRV8329 has 2 variants: the DRV8329A (which supports PWM Mode 6x) and the DRV8329B (which supports PWM Mode 3x). 

At the moment only the DRV8329A variant is available as specified by the following:

I am using DRV8329A, so it only 6x PWM is available, which I used in analysis.

Best Regards

Sal

Hi Sal,

Sal Ye said:

1. When INHx&INLx is input ahead of DRV powered up, DRV always make itself fault after powered up.

To clarify, is this what is happening?

• DRV is not powered
• INHx and INLx are given some input (one is given high signal, etc.)
• DRV gets powered on 
• Fault occurs

Best,

~Alicia

Hi Alicia,

Yes, it is exactly what happened. You can try below signal for verification:

(Green is OUTA; pink is GHA; blue is GLA; Other INHx/INLx is no input)

With the signal I posted, every time when I power up, DRV is set fault, and only when I give a quick low logic pulse to nSLEEP can I release the error.

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Then, if I try the signal below, few times DRV is set fault when I power up, and more often it runs normal.

(pink is IHA; blue is ILA; Other INHx/INLx is no input))

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Note: The test result is get from DRV8329AEVM.

Best Regards

Sal

Hi Sal,

Sal Ye said:

OUTA:

Pink: OUTx (OUTA)    Blue: GND(not used)

You were asked to clarify if the pink waveform was GHA or GLA, but your answer was OUTx (OUTA). This driver is a gate driver, and so there is no such thing called OUTA output. You are a Ti engineer and it seem carelessly respond to other people trying to help you, wasting their time.

Brian 

Hi Sal,

Sal Ye said:

When I set the DRV8329AEVM board input as below:

 (Green is OUTA; pink is GHA; blue is GLA; all connected to GND)

So, considering there is no load for OUTA, so capacitor make the voltage maintain. Does this make sense?

Let's look at what you wrote and the captured waveform:

1. it is not clear what voltage is OUTA waveform -- is it 0v or high voltage? We don't even know what is the voltage applied to the upper FET Drain (PVDD) -- 24v or 60v or anything?

2. "(Green is OUTA; pink is GHA; blue is GLA; all connected to GND)"

all connected to GND? or all signals are referenced to GND?

3. Pink waveform (GHA) is switching about 5v rail to rail, and again, without knowing the lower rail voltage, I would assume it's switching from 0v to 5v, which is totally wrong for GHA output.

4. Blue or GLA: is it 0v or 5v logic? I can't tell from the scope pic.

"Does this make sense?"

It makes zero sense to me reading this.

Brian

Hi Brian,

Let me clarify it.

1. I am using DRV8329AEVM, so you can find the OUTA in PCB board. Meanwhile, it will be connected to SHA.

Brian Dang said:

This driver is a gate driver, and so there is no such thing called OUTA output. You are a Ti engineer and it seem carelessly respond to other people trying to help you, wasting their time.

2. It is high voltage, because you can find it in waveform that it is ~7V (Green one, OUTA). Therefore, it can be inferred that the bus voltage is 7V, which is PVDD. 

Brian Dang said:

1. it is not clear what voltage is OUTA waveform -- is it 0v or high voltage? We don't even know what is the voltage applied to the upper FET Drain (PVDD) -- 24v or 60v or anything?

3.Sorry for the description not precise. I mean that all signal is reference to GND.

Brian Dang said:

2. "(Green is OUTA; pink is GHA; blue is GLA; all connected to GND)"

4.The pink waveform reference low voltage is not display, and it is the same as blue signal, I think it can be recognized so I have not comment on it. In the waveform, GHA is switching from 7V to (7+5)V. Then, I think it should be correct.

Brian Dang said:

3. Pink waveform (GHA) is switching about 5v rail to rail, and again, without knowing the lower rail voltage, I would assume it's switching from 0v to 5v, which is totally wrong for GHA output.

5.I think it is clearly in the scope waveform that blue one (GLA) is 0V, can you clarify why it is misleading?

Brian Dang said:

4. Blue or GLA: is it 0v or 5v logic? I can't tell from the scope pic.

6. In the waveform, we can know that the OUTA (SHA)  is switching from H to Hi-Z, if it has load in output, the output voltage should be like square wave. However, there is no load in OUTA, and then the output voltage  keeps high.

Brian Dang said:

"Does this make sense?"

Best regards

Sal

Sal Ye said:

It is high voltage, because you can find it in waveform that it is ~7V (Green one, OUTA).

Sal Ye said:

5.I think it is clearly in the scope waveform that blue one (GLA) is 0V, can you clarify why it is misleading?

Looking at the pic, how does one tell Green is 7v and Blue is 0v, without knowing where is 0v reference is? No mindreader here. 

Sal Ye said:

In the waveform, GHA is switching from 7V to (7+5)V. Then, I think it should be correct.

If GHA is witching from 7v to 12V -- only 5v for VGS, then it is not correct as I don't think this driver drives the gates with only 5v.

Brian

Hi Brain,

1. 0V voltage.

0V voltage reference is always shown in the left.

2.VGS voltage

I think it is relevant to that there is no load in OUTA (SHA), so the load current is zero, which cause the situation.

If the clarification is not reasonable, I can figure it out later.

Best Regards

Sal