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DRV8962: DRV8432 to DRV8962

Don Labriola1
Prodigy 65 points
Part Number: DRV8962

Looking to try to change design to from DRV8432 (apparently suddenly withdrawn from all documentation and distributors).

First a question on the speed of the current sense output - do you have any documentation on the bandwidth - for example would it be able to show the current with a 1 uS on time (low duty cycle PWM)? Does it show both positive and negative currents (i.e. regen) or only positive currents (must look at both sides to get sign)? The circuitry in the LMD18200T was not sufficiently fast for an accurate reading for such a duty cycle.

Data sheet is preliminary. It seems questionable that each output is given 3 pins to handle the current while the ground pin associated with these same channels have only a single pin per channel which would be carrying up to 10A. I would think that two pins for the output and two for the associated ground would more easily allow the per channel grounds to have appropriately sized traces and package pins for the higher currents. They are adjacent so this is just a documentation and wire bonding change. It would allow much wider traces to handle the current levels these devices are describing. The Vin appear to be internally bussed, so the 4 power pins should be able to share the current - especially when driving motors where not all outputs are simultaneously sourcing current. 

Do these parts handle short circuits without the need for the external inductor needed on the DRV8432 (needed to slow the current rise so the current limit circuitry had time to operate)?

When bridging the outputs (effectively parallel for higher current), what values of series inductance are suggested to handle the skew in output timing?

Does an over current on one channel set the common fault to disable all four channels (i.e. safely turning off any bridged outputs)?

I'm looking forward to the release of these new drivers. My use is as part of a servo drive: voice coil, 2-phase, and 3-phase. The step motor current control modes do not work in these applications, so the pure PWM input driver is greatly needed. No warning was given on the termination of the DRV8432 and there is a feeling that the previous long lead orders for this part may not be honored, given the complete removal of all data sheets and references from TI and from distributors within 48 hours!

Thanks

  • 0
    TI__Mastermind 29655 points

    Hello Don,

    Thank you for your interest with the DRV8962. In this integrated driver device current sensing is done only on the high-side FET, so sensing is in one direction only. Please see snippet below. While we do not have a datasheet specification for bandwidth of the IPROPIx it is an > 1 MHz type of response we get from the analog current mirror. 

    For this specific question, "for example would it be able to show the current with a 1 uS on time (low duty cycle PWM)?" For this scenario we'll have to consider the IPROPIx timing diagram. Please refer to the second snippet from the datasheet. Immediately after INx goes high, IPROPIx is blanked for tBLK which is typically 1.5us with roughly a +/- 20% variation for min and max. In addition to this blanking time there is also a path delay for the IPROPIx which is not currently shown in the preliminary datasheet. This would account for the IPROPIx settling time. From the timing diagram the path delay time starts in parallel with the tBLK. Combined value would amount to; with a best case of ~ 2us and worst case of 3.5us for the output to appear on IPROPIx. 

    If the output on IPROPIx is considered for determining the input PWM duty cycle in closed loop one more parameter in the timing, the deglitch time tDEG must be considered as well, which is 0.5 us typical with a +/- 20% variation for min and max. This is shown in the timing diagram; starts after the voltage on the IPROPIx pin reaches VREF value for Itrip current regulation. 

    For the question on the GND pin, while it appears to be skewed from the number of output pins a lot of engineering decisions have gone into this device design which includes proper sizing of bonding wires to support the low Rdson specified in the device datasheet. The output current specifications have been characterized for the specified comprehensive operating conditions..   

    Regarding short circuits handling, or in other words over current protection OCP, tOCP delay time must be taken in to account. If the low impedance short results in very high current (much higher than IOCP for the specific IC package) within the tOCP time window an inductance in the path would slow it down to not allow for any damages during this delay time. For any low Rdson output FET protection this would be a key aspect to consider especially at higher supply voltages the output current could rise very fast resulting in a very quick thermal hot spot that could permanently damage the device. Only the half-bridge experiencing the overcurrent will be disabled, rest of the half-bridges will function normally.

     

    Regards, Murugavel 

  • 0 in reply to Murugavel4637
    TI__Mastermind 29655 points

    Hello Don,

    I'm checking back with you on this. I hope you got your questions answered. Thanks.

    Regards, Murugavel