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Original question:

DRV8824: nRESET timing relative to nSLEEP/nENBL

DRV8824: Strange Fault Waveforms

Naizeng Wang
Expert 5430 points
Part Number: DRV8824

Hi team,

Customer captured a strange waveform as below. CH1 is fault, CH2 is A phase current and CH3 is B phase current. While the A phase current exceed the OCP threshold(1.8A min), the fault pin is pulled low. The strange point is that the fault pin is pulled up later. As you know, the device will remain disabled until either nRESET pin is applied, nSLEEP is toggled low and high, or VMx is removed and re-applied. In above test, those 3 conditions didn't happen but fault is pulled up. Could you please explain it?

  • 0
    TI__Mastermind 44525 points

    Hi Naizeng,

    Thanks for contacting us. You mentioned phase A current exceeded the OCP threshold. How much was the phase A current? I am unable to gauge it accurately from the scope capture. Is the time/div set at 500us, please confirm. Does this happen with only one device, customer PCB or DRV8824EVM? Can you swap the windings connection and get another capture to see Phase B current behaves the same way. Why is Phase A current looking higher pk-pk compared to Phase B in the scope capture? Could you please share the driver schematic?

    Note that in this device each output has independent current limit circuit that looks at Vds irrespective of the sense resistors. So it is possible for one FET to  be current limited based on its Vds voltage drop. Likely this was what the customer was observing. But we need to verify to confirm what was happening.

    Regards, Murugavel

  • 0 in reply to Murugavel4637
    TI__Mastermind 44525 points

    Hi Naizeng,

    Do we have any updates from the customer? If no further questions please close this thread from your end.

    Regards, Murugavel