DRV8308: Register data isn't written by SPI.

We have very limited support for this device as this is very old device. We would highly recommend checking our Motor drivers site (https://www.ti.com/motor-drivers/brushless-dc-bldc-drivers/overview.html) which can help you pick the right device. 

We have already decided to use DRV8308, so we would like to get your answer.

Thank you for your cooperation.

I would need some time to review your question. I will get back to you next week. 

Hi Vishnu san,

Thank you. I got it. We look forward to your investigat result.

Thanks for your patience

Hi Vishnu san,

Are you already finished your consideration?

We look forward to your information.

Hi Kunihiro,

What is the frequency of the SPI? What are the pull up resistor values? 

Regards,

Vishnu

Hi Vishnu,

Do you mean SCLK of SPI?  So, the frequency is 667kHz.  

WItch pin should I check?

I meant the SCLK pin 

Hi Vishnu,

Sorry my late reply.
SCLK don't have pull up resistor and pull down resistor. This pin is driven with push pull signal.

What do you think is the probable cause?

Hi Kunihiro,

Vishnu is OOO, returning next week - please anticipate a delayed response and we'll get back to you as soon as our device expert is back in office. 

Best Regards, 
Andrew 

Hi Andrew,

Thank you for follow us.

We'll look forward to receve your answer.

Hi Vishnu,

I have additional question.
I found folloing document(On your datasheet).
Does this mean that if RESET is activated while ENABLE is active, the register will be rewritten to the OTP value after 1 second?
If not 1 second, after how many seconds will the rewriting be completed?

Following document form your datasheet.

Yes, that is correct

Thank you your answer.

So, register must be accessed 1sec after reset is asserted, right?

Hi Vishnu,

I would like to anwer this original message too.

Please confirm following message.

Please refer to table 6.6 in the datasheet for the SPI timing requirements. 

We complied your datasheet. But we couldn't write data to address 0x01.

I understand that the motor driver writes a value to a register when it drops SCS.
Should SCS be lowered immediately after data transfer by SDATAI is completed?

Kunihiro

SCS should be HIGH when the host sends the data to the target device. Please refer to section 7.5.2 in the datasheet for the SPI write operation. 

Regards,

Vishnu

Hi Vishnu,

Thank you reply. I had understood that SCS have to be HIGH.

Should SCS be LOW after the host sends the data to the target device?

Please refer following. The host keep sending HIGH until start of next write cycle.

Kunihiro,

I don't think thee is a standard SPI protocol to pull SCS low after data transaction but I would recommend you to try both options (SCS pulled HIGH and LOW) to know which one works as expected. 

Regards,

Vishnu

Hi Vishnu,

We tried both options SCS pulling low after data transcation and SCS leaving High after data transaction.

As a result, in case of SCS leaving High after data transaction we could not be written correctly.

Is there a guideline for the time from when the data transfer is completed to when the SCS is lowered to LOW?　Refet to following picture.

Will get back to you shortly.

Hi Kunihiro,

SCS can be low immediately after the completion of the 24th clock cycle. I don't think there is any minimum timing requirement here to pull SCS low after transmitting 24 bits. 

Regards,

Vishnu

Hi Vishnu san,

Thank you for your answer.

Is there maximum timing request to pull SCS low after transmitting 24 bits?

In other words, can it be held to pull SCS high for a long time after transmitting 24 bits?

Best regards,

Kunihiro 

There is no specific timing requirement but you may pull SCS low after 2-3 clock cycles of SCLK

Hi Vishnu,

Good evening
There is about 11usec until pulled SCS low after transmitting 24 bits on our system.
In other words, there are 7 SCLKs. 
Can this be allowed?

Hi Vishnu,

Good morning

Thnak you for answer. I got it.

if we any question I will let you know.

Best regards,

Kunihiro Amano