DRV8323: driver failure with GDF and VGS_HA fault

Hello Alexandre,

Thank you for posting to the Motor drivers forum! The following is last reply on why ZX's 8323 was out of service:

"Based on the information it does seem like the damage is internal to the device. The damage seems to be resulting in some leakage current from the high side gate to either the source or ground. Thus it requires more current to counteract the leakage current that is from the damage in order to properly charge up the gate. Once the gate current diminishes to ISTRONG, the leakage current overpowers the gate current and the gate voltage begins to drop. As discussed before, the damage is likely caused from an abs max violation on either the GHx pin or the SHx pin due to transients that occur during switching from high inductance paths on the PCB."

If you don't mind, I have a couple questions to ask regarding your issues. Is this issue just occurring with gate A or with all of the gates? What does your timing look like for CLR_FLT and ENABLE and can you provide me with waveforms? There are some timing specifications on page 18 of DRV832x 6 to 60-V Three-Phase Smart Gate Driver datasheet (Rev. D) (ti.com) that need to be adhered to in order for the driver to function properly.

Best,

Eli

Hello Eli,

Thanks for your feedback.

We're making analysis on gate occurence issue, it will take a little time.

see timing diagram with Enable reset pulse in blue and nFault in green.

May be moisture rate, as it reaches 80% and sometimes more than 90%, can be a factor to increase leakage current. Although board has a conformal coating, connector pins and through hole capacitors are not recovered and so not protected.

We try hard to find a cause.

Best regards,

Alexandre

Hello Alexandre,

To clarify, are you using the SPI or hardware version of the DRV8323? If you are using SPI and set the PWM too fast (under 1 ms after enable is triggered) then that may be the issue. Also, how long is nFAULT low for and would you mind showing me waveforms for INHx and INLx during this period as well if the above doesn't work? 

Best,

Eli

Hello Eli,

We use the DRV8323RS, with SPI.

nFault is erased after an enable reset pulse. But is set again after each restart of the board.

For another type of application, we have thousands of boards working for more than a year without this issue.

And for the application with this issue, 10% of the boards run out of service after 5-6 monthes.

Can the timing really be the cause?

We'll try to show you the waveforms.

Thank you,

Best regards

Hello Alexandre,

Would you be able to show me the layout you've been using for this? Also, are you hitting close to any of the extremes for the operating conditions listed in the datasheet?

Best,

Eli

Hello Alexandre,

Thank you for posting on E2E! If this issue has been solved, please resolve the thread as I will be closing it on my end (you can always open it up again if the issue persists). Otherwise, we believe the issue lies in some violation of the ABS_MAX conditions or operation at the end of the device's recommended range. This may be caused by design issues in your PCB layout. Violations of ABS_MAX conditions often cause unnecessary wear to the part which can impede functionality. To find the ABS_MAX and recommended values of your gate driver, please look at Section 7 of DRV832x 6 to 60-V Three-Phase Smart Gate Driver datasheet (Rev. D) (ti.com). If you have any other questions, feel free to create another E2E post.

Best,

Eli