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DRV8832: PWM at motor start

Peter Sterrantino
Prodigy 30 points
Part Number: DRV8832

Data sheet says:

Note that when transitioning from either brake or sleep mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle slowly ramps up to
the commanded voltage. This can take up to 12 ms to go from sleep to 100% duty cycle.

Is this always the case? I have Vref connected to Vset to force 100% duty cycle as described as below in the data sheet:

Note that if the programmed output voltage is greater than the supply voltage, the device will operate at 100%
duty cycle and the voltage regulation feature will be disabled. In this mode the device behaves as a conventional
H-bridge driver.

I am seeing unwanted PWM activity at motor start up that i would like to eliminate. 

  • 0
    TI__Mastermind 37683 points

    Hello Peter,

    Peter Sterrantino said:
    Is this always the case? I have Vref connected to Vset to force 100% duty cycle as described as below in the data sheet

    I will investigate if this delay is expected. I'll get back to you with a reply within 24 hours

    Peter Sterrantino said:
    I am seeing unwanted PWM activity at motor start up that i would like to eliminate. 

    What behavior are you observing? is the output not operating at 100% duty cycle? 

    Regards,

    Pablo Armet

  • 0 in reply to Pablo Armet
    Prodigy 30 points

    Hi Pablo, 

    I am observing PWM activity at motor start (purple trace is motor current measured across the sense resistor). Note approximately 12ms PWM start time before it goes to full duty cycle. Second scope shot is expanded timescale of the first showing approximate PWM frequency.   

    Pete

  • 0 in reply to Peter Sterrantino
    TI__Mastermind 37683 points

    Hi Peter,

    Thank you for the waveforms. I have a better understanding of the problem now. 

    There will be some delay as the PWM ramps up to 100% duty cycle. There can be many factors affecting this delay. But what you are seeing is within expected value. Is this delay a concern in your design?

    Regards,

    Pablo Armet