The stepper driver DRV8434A should be operated in "stall threshold" mode, i.e. STL_MODE = 1, STL_TH = input. For maximum flexibility , I would like to have the threshold voltage generated by the FPGA via a PWM - for this, the largest possible capacitance at the STL_TH pin would be an advantage. However, the data sheet states:
Does this limit of up to 1nF also apply in stall threshold mode, where the pin is an input?
Thanks and bye
Hanno
Hey Hanno,
I believe yes this 1nF limit applies whether the pin is an input or an output. In 7.3.9.4 Stall Detection it mentions the 1nF capacitor requirement in the sentence immediately after saying it can be an input/output, and it doesn't specify a single mode.
That said, you could certainly test it with our evaluation module (DRV8434AEVM) and replace C12 with your desired capacitor values to test it. It's possible a larger capacitor value will make the stall learning routine not work reliably, or make stall detection unreliable, or it might just take longer for the device to detect a change in the threshold. I'm not sure.
Regards,
Jacob
