DRV8353R: SPI comm failure issue for DRV8353

Hi TI,

We failed to control the register through the SPI interface during the use of DRV8353RS, please help us check that there may be a problem with that step.
We use the 4 GPIOs of STM32F103 to simulate the SPI interface, which is connected to the clock, chip select, the GPIO of MOSI is set as output, and the GPIO connected to MISO is set as input.
enable high
chip select low
clock low
When reading registers 0h, 4h, and 5h, the output of DRV8353RS is all high level, and it feels like DRV8353 has no response at all.
04h The register reading communication waveform is as follows. The yellow in the first picture is the chip select and the blue is the clock; the yellow in the second picture is the clock and the blue is MOSI; MISO is always high
The data of MOSI is 0xA000,

Thanks,

                                                                    Tandi
                                                 OKAWA MOTOR, ShangHai, China