DRV8353R: SPI configuration failed

Hey Cherry,

Can the customer check thr SPi programming section of the DS (page 54) to check if they are reading the signal at the correct timing?

Best,

Akshay

Hi Akshay,

Thank you for the support.

The customer has modified the code. The current case is that the data read back is always 0xffff. This means that the open-drain output of the chip SDO has not turned on. The SDI pin is measured with an oscilloscope and it can be seen that it is always high.

The A channel is chip select and the B channel is clock:

The A channel is the clock signal and the B channel is the signal STM32 writes to the DRV8353:

And the test code is as follows:

Thanks and regards,

Cherry

Hi Akshay,

Akshay Rajeev Menon said:

I am suspecting that the customer is sending signals at the wrong timing .

Dose it refer to the clock polarity and phase are not correct? 

May I know what S/W are being used at your end?

Thanks and regards,

Cherry

Hi Akshay,

The customer uses an oscilloscope to see that the waveform is indeed sampling on the falling edge of the clock, and the clock phase looks fine:

The idle clock is in a low state and the polarity also seems good:

Thanks and regards,

Cherry

Hey Cherry, 

When writing to the register the write bit is 0 not 1 as seen in the waveform attached. Also would it be possible to see all the spi lines in a single scope shot?

Please note that the data is propagated on the rising edge of sclk not the falling edge.

Best,
Akshay