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Original question:

DRV8432 devices on existing design - what are the options?

DRV8412: RESET_AB

justin hustee
Prodigy 30 points
Part Number: DRV8412

According to DRV8412 datasheet (p13), "In OC latching shut down mode, the CBC current limit and error recovery circuits are disabled and an overcurrent condition will cause the device to shutdown immediately. After shutdown, RESET_AB and/or RESET_CD must be asserted to restore normal operation after the overcurrent condition is removed." It states that RESET_AB need set to be "low" to restore normal operation after OC condition.

According to DRV8412 datasheet (p14), "OTSD is latched in this case and RESET_AB and RESET_CD must be asserted low to clear the latch." the same as the previous statement that  RESET_AB need "low" to restore normal operation after a shutdown due to FAULT event. But in the same page (p14), "asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high- impedance state", it means setting RESET_CD low causes All 4 FETs in high-impedance state, which is clearly not the normal operation.

According to DRV8412 datasheet (p14), "A rising-edge transition on reset input allows the device to resume operation after a shut-down fault. For example, when either or both half-bridge A and B have OC shutdown, a low to high transition of RESET_AB pin will clear the fault and FAULT pin; when either or both half-bridge C and D have OC shutdown, a low to high transition of RESET_CD pin will clear the fault and FAULT pin as well. When an OTSD occurs, both RESET_AB and RESET_CD need to have a low to high transition to clear the fault and FAULT signal", it states that RESET_AB need a transition from low to high to clear the latch and restore the normal operation.

The above statements seem be against each other. My question is 

1) when signal is "RESET_AB" and "RESET_CD" in the normal operation?

2) what signal or what signal change is needed to clear FAULT latch and restore the normal operation?

It would be appreciated if you could show the "RESET_AB" signal corresponding the sequence "normal operation", "faulty event", "go back to operation" in a diagram. Thanks

  • 0
    TI__Mastermind 23421 points

    Hey Justin,

    I think basically the functionality of the RESET_AB/CD can depend on which protection tripped it.  

    One note - when it says "all four power-stage FETs" it means the 4 internal FETs used for outputs A and B or C and D, not all 8 internal FETs collectively.  Hence resetting AB vs CD separately.  

    OCP Protection shutdown for AB in OC latching (OCL) shut down mode

    • Device state: shutdown, all outputs HI-Z
    • Reset:  set RESET_AB and/or RESET_CD LOW (after overcurrent condition removed)

    OCP Protection shutdown for AB in cycle-by-cycle (CBC) current limiting mode

    • Device state: device turns off affected FET and turns on the other FET in half-bridge until next PWM cycle.
    • Reset: cycle PWM_A or PWM_B to resume normal operation

    OTP Overtemperature protection shutdown OTSD latched

    • Device state:  all outputs Hi-Z, nFAULT LOW
    • Reset:  Set both RESET_AB and RESET_CD LOW to clear latch

    General reset: follow the final paragraph you linked.  The Low-to-High transition clears a fault. Let me know if this wasn't clear

    At any time, if RESET_AB or RESET_CD are low, all four outputs become high-impedance.  Although not specifically required, holding RESET_AB and RESET_CD in a low state while powering up the device is recommended. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.

    Regards,

    Jacob