Hello experts,
Hope you are doing well.
Our customer have some questions:
1. What is the time or time stage it takes for the chip to overcurrent from Iout to Toff shutdown in response from Itrip? (from comparator to core output control signal)
2. How many times of Toff would last under Itrip be triggered, is there any limit on the number of times?
Thanks.
Hi Daniel,
1. What is the time or time stage it takes for the chip to overcurrent from Iout to Toff shutdown in response from Itrip? (from comparator to core output control signal)
In the SPI variant of the DRV8243-Q1 the over current protection deglitch times (tOCP) are configurable.
From the image below, the tOCP is the time after the ITRIP threshold is breached and can be adjusted in the register settings.
After the OCP fault has been confirmed, the device will attempt an automatic retry time period to determine if a short actually occurred.
From your post above, the device will experience a double of the tOFF time for any current values extending over a single tOFF time.
2. How many times of Toff would last under Itrip be triggered, is there any limit on the number of times?
There is not a specific limit to the number of times for triggering TOFF and ITRIP. However, when the current is hitting ITIP consistently then the risk of over temperature comes into play. The ITRIP threshold is ideally intended for large inrush currents that occur during motor start-up or stall.
Best,
David
