DRV8701: PWM waveforms appear when H-bridge is driving BDC, not in regulation and under load

Cherry Zhou

Part Number: DRV8701

Hi Team,

With the DRV8701P chip, IN1 is high, in2 is low, and the motor is operating without load. MOS tube gate is very high at 1.6A. Motor loaded with 4.2A current, Ichop set to 6A.

Issue: The gate will have a regular PWM wave.

The customer suspects that it's due to the internal automatic adjustment of the chip. If so, could you help share the adjustment method or discipline? The load current has not reached Ichop, and the internal regulation of the chip should not work, right?

Could you help check this case? Thanks.

Best Regards,

Cherry

over 1 year ago

0 Keerthivasan Kumanan over 1 year ago

TI__Mastermind 19575 points

Hi Cherry,

Can you tell me what the scope captures correspond to and if they are using our EVM or if it is their own board. If it is their own board can you send a schematic, so I can take a look.

Best,

Keerthi

0 Cherry Zhou over 1 year ago in reply to Keerthivasan Kumanan

TI__Mastermind 22235 points

Hi Keerthi,

Thank you for the support.

Keerthivasan Kumanan said:
Can you tell me what the scope captures correspond to

It's the waveform of the pre-drive GH port. According to the programd procedure, GH should be always pulled high, but in fact GH is partially low then resulting in MOS being turned off. Then Ichop was increased to 10A, GH was good at 4.3A load and being pulled up all the time.

Thanks and regards,

Cherry

0 Keerthivasan Kumanan over 1 year ago in reply to Cherry Zhou

TI__Mastermind 19575 points

Hi Chery,

Give me 24 hours to look into this and respond.

Best,

Keerthi

0 Keerthivasan Kumanan over 1 year ago in reply to Keerthivasan Kumanan

TI__Mastermind 19575 points

Hi Cherry,

Just to clarify. They are trying to run it at 100 % duty cycle and that is why GH should always be high. Can they also capture their IN1 and IN2 waveforms to make sure they are also truly 100 and 0 % duty cycle. Can they try this with our EVM as well to see if it is an issue with their board. I will also try it out on my end.

Best,

Keerthi

0 Cherry Zhou over 1 year ago in reply to Keerthivasan Kumanan

TI__Mastermind 22235 points

Hi Keerthi,

Thank you for the clarification.

Keerthivasan Kumanan said:
Can they try this with our EVM as well to see if it is an issue with their board.

They don't have EVM so are not able to have a try on it.

Keerthivasan Kumanan said:
Can they also capture their IN1 and IN2 waveforms to make sure they are also truly 100 and 0 % duty cycle.

Please see the waveforms:

The waveform with no load is as follows:

The waveform with heavy load is as follows:

The zoomed in waveform with heavy load is shown below:

Thanks and regards,

Cherry

0 Jacob Thompson over 1 year ago in reply to Cherry Zhou

TI__Mastermind 23441 points

Hey Cherry,

Can you confirm they have the recommended 0.1uF charge pump capacitor between CPH and CPL? Incorrect charge pump value could cause the driver to not be able to maintain 100% duty cycle

Cherry Zhou said:
They don't have EVM so are not able to have a try on it.

They might want to order an EVM to test it on.

Is this a new design? If so, I recommend looking into our newer gate drivers such as the DRV8706-Q1, as it has many improvements over the DRV8701 (our first gate driver).

Best,

Jacob

Motor drivers

Motor drivers forum

DRV8701: PWM waveforms appear when H-bridge is driving BDC, not in regulation and under load