DRV8889-Q1: Motor drivers forum

Chase Jeong

Part Number: DRV8889-Q1
Other Parts Discussed in Thread: DRV8462

Dear TI experts,

My customer tests DRV8889-Q1 with their own PCB. and there is a heat when motor is operated.

My customer says that the heat is about 60℃. I want to know that this temperature is reasonable when DRV8889 is working.

the condition is as below ;

Vref :3V

TQA DAC : 62.5%

Current : 0.6A

Step : 1/16

And here are more questions ;

1. Can I turn off no.1 FET and turn on no.2 FET when motor is not rotated?

2. I only saw the SPI timing requirements on section 6.6 on the datasheet. Do you have timing diagram chart about SPI timing?

3. I found a register about stall threshold.(STALL_TH)

If I set this value, Can I see stall detection if this value is under STALL_TH?

What should I set STALL_TH if I want to see stall detection even light load? (high STALL_TH or low STALL_TH?)

Best regards,

Chase

over 1 year ago

0 Murugavel4637 over 1 year ago

TI__Mastermind 44325 points

Hi Chase,

Thanks for the post. What is the supply voltage that was used? For 0.6 A IFS I do not expect 60C with Ta = 25C. This could be mainly because of the PCB layout. What package of the device was used. The QFN package would run hotter than the HTSSOP.

1. The FETs are driven by the integrated indexer. The indexer table is provided in page-17 of the datasheet, https://www.ti.com/lit/ds/symlink/drv8889-q1.pdf. FETs cannot be individually controlled in this device.

2. See Figure 7-32. SPI Transaction in the datasheet page-44.

3. Yes this register is meant for setting the STALL_TH. There is another register TRQ_COUNT. When TRQ_COUNT < STAL_TH a stall will be detected. STALL_TH can be automatically set by using a learn stall - or - manually entered usually < or = 50 % of the TRQ_COUNT at the target uSteps and STEP rate of the motor running with no load or normal load.

Regards, Murugavel

0 Chase Jeong over 1 year ago in reply to Murugavel4637

Mastermind 7395 points

Dear Murugavel,

Thank you for your support.

Could you check the layout of my customer? I could not find any problem.

Best regards,

Chase

0 Murugavel4637 over 1 year ago in reply to Chase Jeong

TI__Mastermind 44325 points

Hi Chase,

I'm unable to interpret the details of the layout specifically with the thermal vias. I assume they follow the datasheet recommendations. Also our EVM layout is posted on the EVM webpage for download and reference. Below is the datasheet recommendation. We use 2oz copper for the top and bottom layer for better thermal dissipation.

Assuming the layout has no issues another parameter to look at is the Slew Rate setting. The default value is the slowest. Slow slew rate will have maximum switching losses and cause higher power dissipation with current regulation chopping. Customer can try faster slew rates to minimize switching loss and improve thermal performance. Faster switching will impact EMI performance. Customer has to find the right setting of the SR that offers minimum switching loss and desired EMI performance.

Regards, Murugavel

0 Chase Jeong over 1 year ago in reply to Murugavel4637

Mastermind 7395 points

Dear Murugavel,

Thank you for your support.

1. I will test about slew rate with my customer for thermal issue.

2. I checked SPI transaction diagram (page 44 on the datasheet) but there are not any numbers. it is very hard to match the number and diagram(graph)

Do you have any timing diagram of DRV8889-Q1 like below? (timimg diagram with numbers)

Best regards,

Chase

0 Karan Doshi over 1 year ago in reply to Chase Jeong

TI__Intellectual 2540 points

Hi Chase,

DRV8889-Q1 supports a wide variety of SPI frequencies. Please refer to Table 6.6 on page 9 of the DRV8889-Q1 datasheet for minimum timings on each of the signals. You can refer to this diagram from DRV8462 for description of various parameters.

Regards,

Karan Doshi