Hello,
In the application note it specifies 1uF capacitor from Vgls to ground, 1uf capacitor from Vcp to Vdrain, and 47nF capacitor between Cph and Cpl. Can larger capacitors be used in these locations? I am driving four FETs in parallel each with each FET having 166nC of total gate charge. I am seeing dips in Vgls that I'd like to minimize by using more capacitance but I'm not sure what range of capacitance is OK for the linear regulator that drives Vgls.
I have the same question concerning Vcp capacitor as I'd guess its having the same issue.
Thanks - Bruce
