Hello Team,
what would be the resolution of the PWM between 90% and 100%?
Is there a restriction on minium off-time in our gate drivers?
We know that some architecture when achieving 90% duty cycle they skip directly to 100% but this in some application critical.
So, do we have more description about the behavior between 90% and 100% duty cycle for DRV8702?
Many Thanks
Josef
Hi,
This device does not have internal PWM generator. Therefore MCU provide PWM signal then DRV provides driving output.
Output can provide 90-100% duty cycle. DRV will react to increase/decrease output based on PWM input from MCU.
Depending on rise/fall time, some high duty% input PWM from MCU will stack 100% output.
This is not DRV's performance. All motor drivers should have this behavior.
regards
Shinya Morita
