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DRV2624: Pulling I2C pins high when VDD is 0V

Cameron Wutzke
Expert 3532 points
Part Number: DRV2624

Hey Folks,

What drives this requirement internally and what is the effect of pulling these pins to 1.8V when VDD is disconnected?

Thanks!

Cameron

  • 0
    TI__Genius 17820 points

    Hi Cameron, 

    I believe if VDD is lower than the SCL and SDA pins there would be some reverse current that could damage the device. Instead of turning off the DRV2624 device with VDD, you could pull down the NRST pin which puts the device into its lowest power state (~105nA). In doing this the VDD voltage > SCL and SDA voltage condition is met and the device is in a shutdown state.

    Regards,
    Sydney Northcutt 

  • 0 in reply to Sydney Northcutt
    TI__Expert 3532 points

    Thanks Sydney,

    I2C voltage levels will either be 1.8V or 3.3V. Most likely 1.8V

    • What would be the expected failure mode if SDA/SCL > VDD?
      • Presumably the leakage current is through ESD protection? If so, is there a max current spec that wouldn’t damage the device? (aka what could we safely get away with for VDD if SDA is 1.8 or 3.3?)
    • Holding NRST low removes this concern? That is, if we always hold NRST low when VDD = 0V, while SDA/SCL have 1.8/3.3V, is this a problem?

    I was playing around with my eval board and VDD = GND while SDA/SCL = 1.8V I don't see issues. But, I feel uncomfortable giving final thumbs up without understand the internals

    Thanks!

    Cameron

  • 0 in reply to Cameron Wutzke
    TI__Expert 3532 points

    And one thing I forgot to ask- diving into VDD supply, would you expect "crisper" feeling LRA with higher VDD voltage? I don't have a good way to test this currently so I'm leaning on you Slight smile

    Thinking about running this at 5.0V with goal of improving LRA feeling

  • 0 in reply to Cameron Wutzke
    TI__Genius 17820 points

    Hi Cameron, 

    No, we do not have a max current spec for this. Having the SDA and SCL at a higher voltage than VDD would not immediately damage the device but will damage the device over the long term if this is consistently done, which is why we advise against it. If there was a spec that would safely get around this, we would recommend that.

    I should first ask why you are wanting to turn VDD to 0 V while SDA and SCL are on? I assume to turn off the device when it is not being used so it doesn't pull unnecessary current, but the I2C line needs to stay active to control other devices, correct? If so, that is what the NRST pin is for. VDD still needs to be supplied to the device, but the NRST pin puts the device into a shutdown state - drawing only nA of current! It is turning off all blocks inside the device, even I2C communication. If I am misunderstanding the application, please correct me.

    Having a larger VDD will allow you to have a larger voltage on the output, so it will allow you to have a stronger vibration, but not necessarily a "crispier" feeling. A crispier feeling is executed by integrating the auto over drive and auto braking features. 

    Regards,
    Sydney Northcutt

  • 0 in reply to Sydney Northcutt
    TI__Expert 3532 points
    Sydney Northcutt said:
    I should first ask why you are wanting to turn VDD to 0 V while SDA and SCL are on?

    I misunderstood use case before, I can clarify … use case is VDD = 5V while SDA/SCL = 1.8V 

  • 0 in reply to Cameron Wutzke
    TI__Genius 17820 points

    Hi Cameron, 

    Ah I see. This is a valid use case as VDD V > SDA/SCL V. 

    Regards,
    Sydney Northcutt 

  • 0 in reply to Cameron Wutzke
    TI__Expert 3532 points
    Cameron Wutzke said:
    • Holding NRST low removes this concern? That is, if we always hold NRST low when VDD = 0V, while SDA/SCL have 1.8/3.3V, is this a problem?

    Would you mind commenting on this? My understanding it yes, it is a problem 

  • 0 in reply to Cameron Wutzke
    TI__Expert 3532 points

    and if our pull-ups are 100k to 1.8V, 1.8uA would theoretically sink through SDA/SCL -> VDD through those ESD diodes (my assumption the concerning path is ESD diodes). Could we dive into the IP block to see how much current we can safely sink there? 

  • 0 in reply to Cameron Wutzke
    TI__Genius 17820 points

    Hi Cameron, 

    I set some time up with my team to discuss this further today and will provide an update this evening. 

    Regards,
    Sydney Northcutt 

  • 0 in reply to Sydney Northcutt
    TI__Expert 3532 points

    Thank you Sydney! I’ll be at HQ later so feel free to phone me in or send anything calendar. Learning new stuff about designs is the best part of this job

    the I2C lines are pulled up 2.2k to 1.8V. We have the ability to adjust that pull up resistance. They didn’t like my idea of load switches to isolate that much (extra BOM cost + mm^2)

    we have a fallback plan, I’m suggesting something like this if we REALLY cannot sustain 1.8uA (if switched to 100k pull-ups for example) 

  • 0 in reply to Cameron Wutzke
    TI__Genius 17820 points

    Hi Cameron, 

    Agreed!

    I was directed to another person on our team who will have more insight. Sorry for the delay.

    Regards,
    Sydney Northcutt