Tool/software:
We are using the DRV8353HMRTAT chip in our module. We are running a 48v motor using an H bridge and 2 of the phases of the drive chip. We have the control set to 6 x PWM. When running clockwise we have the INHA and INLA running a complimentary PWM. On the other phase we we have INHB low and INLB high. The shunt resistors are below the low side gate and ground. So when we are running clockwise the flow path is from the GHA gate to the GLB gate through the motor and hence we are able to read current using the Shunt 2 circuit. When operating counter clockwise this is all reversed and we are able to read the current through the Shunt 1 circuit.
We are using a hard wired gain setting to the GAIN pin, tied to ground so gives a 5:1 gain.
We have had a problem that on some of our modules we get incorrect readings for the Shunt 1 current reading. We have probed the boards and the voltage across SPx and SNx is exactly as we expect for the current which is flowing. For Shunt 2 the SOB reading is exactly 5 times the SPB - SNB as we expect. But for shunt 1 the SOA reading is no where near this. It is closer to 1.5:1 times the SPA-SNA.
As we are only able to set one GAIN for the chip it seems pretty conclusive there is a problem with the chip.
The majority of modules do not have this issue, but we do have several which do. And it is always the Shunt1 output which is faulty. On the faulty modules we can swap out the chip and then everything is fine. If we re-install the "Faulty" chip, the fault is there again.
So far we have not been able to identify whether the chips had the fault when supplied, became faulty when installed, or became faulty in use. We are putting in place additional tests on built units before they are released, but we do not know if we have a potential issue of impending failures in the field.
So I have a few questions;
A) Has anyone else observed this type of behaviour?
B) Is this a known issue with these chips?
C) What are the failure modes which could lead to this behaviour?
D) Is there a known way to cause the chips to fail in this manner? I note that SOA is adjacent to VREF, so things like a temporary short between those pins, that sort of thing.